2024-03-11 05:24:05
The Synopsys LPDDR5/4/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-in-package applications requiring high-performance LPDDR5X, LPDDR5, LPDDR4, and LPDDR4X SDRAM interfaces operating at up to 6400 Mbps. With flexible configuration options, the LPDDR5/4/4X PHY can be used in a variety of mobile applications supporting LPDDR5X, LPDDR5 and/or LPDDR4/4X SDRAMs, precisely targeting the specific power, performance, and area (PPA) requirements of these systems.
Optimized for high performance, low latency, low area, low power, and ease of integration, the LPDDR5/4/4X PHY is provided as hardened IP components (macrocells) to facilitate the following types of signals:
- Single-ended Command/Address (C/A) and Data (DQ) signals
- Differential signals (clock, data strobe, and WCK signals)
- CMOS logic-level based C/A signals
The macrocells include fully integrated IOs and are easily assembled into a variety of configurations supporting a wide range of SoC DRAM interface requirements. Supporting the GDSII-based PHY is the RTL-based PHY Utility Block (PUB) that features Synopsys’ unique firmware-based training capability. In addition to training the interface after boot-up, the PUB contains the configuration registers for the PHY, performs periodic delay line compensation against voltage and temperature drift, performs DRAM retraining, and facilitates ATE testing and interface diagnostics. The LPDDR5/4/4X PHY includes a DFI 5.0 interface to the memory controller and can be combined with the Synopsys LPDDR5/4/4X Controller for a complete DDR interface solution.
Synopsys LPDDR5/4/4X PHY IP Datasheet
Highlights
Products
Downloads and Documentation
- Supports JEDEC standard LPDDR5X, LPDDR5, LPDDR4 and LPDDR4X SDRAMs
- Support for data rates up to 6400 Mbps
- Designed for rapid integration with Synopsys’ LPDDR5/4/4X controller for a complete DDR interface solution
- DFI 5.0 controller interface
- PHY-independent, firmware-based training using an embedded calibration processor
- Optional dual channel architecture for LPDDR5X/LPDDR5/4/4X modes, which facilitates two independent channels in less area versus two independent PHYs
- Support for DFI-based low-power modes and lower-power sleep and retention modes
- Support for up to 15 trained states/frequencies
- Flexible implementation to support Package-On-Package (PoP) or discrete DRAM-on-PCB systems with optimized PHY architecture
- Built-in anti-aging features to prevent effects of NBTI & HCI
Description: |
LPDDR5/4/4X PHY - GF 12LP+ |
Name: |
dwc_lpddr54_phy_gf12lpp18 |
Version: |
1.00a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
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Application Notes DesignWare Cores LPDDR5/4/4X PHY IBIS Model Application Note (Version 1.41a) ( PDF | HTML )
DesignWare Cores LPDDR5/4 PHY OCC Implementation Using Internal PLL Application Note (Version:1.10a) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY ATE Firmware Application Note (FW Version: C-2021.03) ( PDF )
DesignWare Cores LPDDR5/4/4X PHY Diagnostics Firmware Application Note (FW Version: C-2021.03) ( PDF )
DesignWare Cores LPDDR5/4/4X PHY Interconnect Signal and Power Integrity Guidelines Version 1.20a ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY PHYInit Software Overview Application Note ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY Quickboot Application Note (Version 1.40a) ( PDF )
DesignWare Cores LPDDR5/4/4X PHY Training Firmware Application Note (FW Version: C-2021.03) ( PDF )
DesignWare Cores LPDDR5/4/4X PHY coreKit User Guide (coreKit Version:2.20a) ( PDF | HTML )
DesignWare Cores LPDDR54 PHY CTB and Verification Application Note (Version 1.01a) ( PDF )
Databooks DesignWare Cores LPDDR5/4/4X PHY for GF12LPP18 Databook (PHY Version: 1.00a) ( PDF | HTML )
Synopsys PHY IP LPDDR5/4/4X PHY Utility Block Databook (PUB Version: 2.20a_d4) ( PDF | HTML )
Implementation Guide Synopsys PHY IP LPDDR5/4/4X PHY Implementation Guide (Doc. Version 2.80a) ( PDF | HTML )
Release Notes DesignWare Cores LPDDR5/4/4x PHY Release Notes for GFLPP18 (PHY Version: 1.00a) ( TEXT )
|
Download: |
dwc_lpddr54_phy_gf12lpp18 |
Product Code: |
F758-0 |
Description: |
LPDDR5/4/4X PHY - GF 12LP+ for Automotive ASIL B Random, AEC-Q100 Grade 1 |
Name: |
dwc_ap1_lpddr54_phy_gf12lpp18 |
Version: |
1.00a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
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Application Notes DesignWare Cores LPDDR5/4 PHY OCC Implementation Using Internal PLL Application Note (Version:1.10a) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY ATE Firmware Application Note (FW Version: C-2023.11) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY CTB and Verification Application Note (CTB Version: C-2023.11) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY Diagnostics Firmware Application Note (FW Version: C-2023.11) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY Interconnect Signal and Power Integrity Guidelines Version 1.20a ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY PHYInit Software Overview Application Note ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY Quickboot Application Note (Version C-2023.11) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY Training Firmware Application Note (FW Version: C-2023.11) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY coreKit User Guide (coreKit Version: 2.30b_d1) ( PDF | HTML )
Databooks Synopsys PHY IP LPDDR5/4/4X PHY Utility Block Databook (PUB Version: 2.30a_d3) ( PDF | HTML )
Synopsys PHY IP LPDDR5/4/4X PHY for GF12LPP18 Databook for Automotive Package Grade 1 (AP) (PHY Version: 1.00a) ( PDF | HTML )
Implementation Guide Synopsys PHY IP LPDDR5/4/4X PHY Implementation Guide (Doc. Version 2.80a) ( PDF | HTML )
Release Notes Synopsys PHY IP LPDDR5/4/4X PHY Release Notes for GF12LPP18 Databook for Automotive Package Grade 1 (AP) (PHY Version: 1.00a) ( TEXT )
|
Download: |
dwc_ap1_lpddr54_phy_gf12lpp18 |
Product Code: |
H754-0 |
Description: |
LPDDR5/4/4X PHY - SS 14LPU for Automotive AEC-Q100 Grade 1 |
Name: |
dwc_ag1_lpddr54_phy_ss14lpu18 |
Version: |
1.00a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
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Application Notes DesignWare Cores DDRPHY Backdoor Support Application Note (Version: 1.10a) ( PDF | HTML )
DesignWare Cores LPDDR5/4 PHY OCC Implementation Using Internal PLL Application Note (Version:1.10a) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY ATE Firmware Application Note (FW Version: C-2023.11) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY CTB and Verification Application Note (CTB Version: C-2023.11) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY Diagnostics Firmware Application Note (FW Version: C-2023.11) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY Interconnect Signal and Power Integrity Guidelines Version 1.20a ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY PHYInit Software Overview Application Note ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY Quickboot Application Note (Version C-2023.11) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY Training Firmware Application Note (FW Version: C-2023.11) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY coreKit User Guide (coreKit Version: 2.30b_d1) ( PDF | HTML )
Databooks Synopsys PHY IP LPDDR5/4/4X PHY Utility Block Databook (PUB Version: 2.30a_d3) ( PDF | HTML )
Synopsys PHY IP LPDDR5/4/4x PHY for SS14LPU18 Databook for Automotive Grade, Grade 1 (AG) (PHY Version: 1.00a) ( PDF | HTML )
Implementation Guide Synopsys PHY IP LPDDR5/4/4X PHY Implementation Guide (Doc. Version 2.80a) ( PDF | HTML )
Release Notes Synopsys PHY IP LPDDR5/4/4x PHY for SS14LPU18 Databook for Automotive Grade, Grade 1 (AG) Release Notes (PHY Version: 1.00a) ( TEXT )
|
Download: |
dwc_ag1_lpddr54_phy_ss14lpu18 |
Product Code: |
F799-0, I370-0 |
Description: |
LPDDR5/4/4X PHY - TSMC 12FFC |
Name: |
dwc_lpddr54_phy_tsmc12ffc |
Version: |
2.80a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
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Application Notes DesignWare Cores LPDDR5/4/4X PHY IBIS Model Application Note (Version 1.51a_d1) ( PDF | HTML )
DesignWare Cores LPDDR5/4 PHY OCC Implementation Using Internal PLL Application Note (Version:1.10a) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY ATE Firmware Application Note (FW Version: C-2022.10)) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY CTB and Verification Application Note (CTB Version: C-2022-10) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY Diagnostics Firmware Application Note (FW Version: C-2022.10) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY Interconnect Signal and Power Integrity Guidelines Version 1.20a ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY PHYInit Software Overview Application Note ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY Quickboot Application Note (Version C-2022.10) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY Training Firmware Application Note (FW Version: C-2022.10) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY coreKit User Guide (coreKit Version:2.30a) ( PDF | HTML )
Databooks DesignWare Cores LPDDR5/4/4X PHY Databook for TSMC12FFC18 (PHY Version: 2.80a) ( PDF | HTML )
Synopsys PHY IP LPDDR5/4/4X PHY Utility Block Databook (PUB Version: 2.30a_d3) ( PDF | HTML )
Implementation Guide Synopsys PHY IP LPDDR5/4/4X PHY Implementation Guide (Doc. Version 2.80a) ( PDF | HTML )
Release Notes DesignWare Cores LPDDR5/4/4X PHY Release Notes (PHY Version 2.80a) ( TEXT )
|
Download: |
dwc_lpddr54_phy_tsmc12ffc18 |
Product Code: |
D774-0 |
Description: |
LPDDR5/4/4X PHY - TSMC 16FFC |
Name: |
dwc_lpddr54_phy_tsmc16ffc |
Version: |
2.30a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
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Application Notes DesignWare Cores LPDDR5/4/4X PHY IBIS Model Application Note (Version 1.51a_d1) ( PDF | HTML )
DesignWare Cores LPDDR5/4 PHY OCC Implementation Using Internal PLL Application Note (Version:1.10a) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY ATE Firmware Application Note (FW Version: C-2022.04)) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY CTB and Verification Application Note (CTB Version: C-2022-04) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY Diagnostics Firmware Application Note (FW Version: C-2022.04) ( PDF )
DesignWare Cores LPDDR5/4/4X PHY Interconnect Signal and Power Integrity Guidelines Version 1.20a ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY PHYInit Software Overview Application Note ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY Quickboot Application Note (Version C-2022.04) ( PDF )
DesignWare Cores LPDDR5/4/4X PHY Training Firmware Application Note (FW Version: C-2022.04) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY coreKit User Guide (coreKit Version:2.20b) ( PDF | HTML )
Databooks DesignWare Cores LPDDR5/4/4X PHY Databook for TSMC16FFC1 (PHY Version: 2.30a) ( PDF | HTML )
Synopsys PHY IP LPDDR5/4/4X PHY Utility Block Databook (PUB Version: 2.20a_d4) ( PDF | HTML )
Implementation Guide Synopsys PHY IP LPDDR5/4/4X PHY Implementation Guide (Doc. Version 2.80a) ( PDF | HTML )
Release Notes DesignWare Cores LPDDR5/4/4X PHY Release Notes (PHY Version: 2.30a) ( TEXT )
|
Download: |
dwc_lpddr54_phy_tsmc16ffc18 |
Product Code: |
D773-0 |
Description: |
LPDDR5/4/4X PHY - TSMC N5 |
Name: |
dwc_lpddr54_phy_tsmc5ff12 |
Version: |
3.00a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
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Application Notes DesignWare Cores LPDDR5/4/4X PHY IBIS Model Application Note (Version 1.51a_d1) ( PDF | HTML )
DesignWare Cores LPDDR5/4 PHY OCC Implementation Using Internal PLL Application Note (Version:1.10a) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY ATE Firmware Application Note (FW Version: C-2022.04)) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY CTB and Verification Application Note (CTB Version: C-2022-04) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY Diagnostics Firmware Application Note (FW Version: C-2022.04) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY Interconnect Signal and Power Integrity Guidelines Version 1.20a ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY PHYInit Software Overview Application Note ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY Quickboot Application Note (Version C-2022.04) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY Training Firmware Application Note (FW Version: C-2022.04) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY coreKit User Guide (coreKit Version:2.20a) ( PDF | HTML )
Databooks DesignWare Cores LPDDR5/4/4x PHY Databook for TSMC5FF12 (PHY Version: 3.00a) ( PDF | HTML )
Synopsys PHY IP LPDDR5/4/4X PHY Utility Block Databook (PUB Version: 2.20a_d4) ( PDF | HTML )
Implementation Guide Synopsys PHY IP LPDDR5/4/4X PHY Implementation Guide (Doc. Version 2.80a) ( PDF | HTML )
Release Notes DesignWare Cores LPDDR5/4/4x PHY Release Notes for TSMC5FF12 (PHY Version: 3.00a) ( TEXT )
|
Download: |
dwc_lpddr54_phy_tsmc5ff12 |
Product Code: |
E377-0 |
Description: |
LPDDR5/4/4X PHY - TSMC N6 |
Name: |
dwc_lpddr54_phy_tsmc6ff18 |
Version: |
1.40a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
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Application Notes DesignWare Cores LPDDR5/4/4X PHY IBIS Model Application Note (Version 1.41a) ( PDF | HTML )
DesignWare Cores LPDDR5/4 PHY OCC Implementation Using Internal PLL Application Note (Version:1.10a) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY ATE Firmware Application Note (FW Version: C-2023.06) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY CTB and Verification Application Note (CTB Version: C-2023.06) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY Diagnostics Firmware Application Note (FW Version: C-2023.06) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY Interconnect Signal and Power Integrity Guidelines Version 1.20a ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY PHYInit Software Overview Application Note ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY Quickboot Application Note (Version C-2023.06) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY Training Firmware Application Note (FW Version: C-2023.06) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY coreKit User Guide (coreKit Version: 2.30b_d1) ( PDF | HTML )
Databooks Synopsys PHY IP LPDDR5/4/4X PHY Databook for TSMC6FF (PHY Version: 1.40a_d1) ( PDF | HTML )
Synopsys PHY IP LPDDR5/4/4X PHY Utility Block Databook (PUB Version: 2.30a_d3) ( PDF | HTML )
Implementation Guide Synopsys PHY IP LPDDR5/4/4X PHY Implementation Guide (Doc. Version 2.80a) ( PDF | HTML )
Release Notes DesignWare Cores LPDDR5/4/4X PHY Release Notes (PHY Version: 1.40a) ( TEXT )
|
Download: |
dwc_lpddr54_phy_tsmc6ff18 |
Product Code: |
E562-0 |
Description: |
LPDDR5/4/4X PHY - TSMC N7 |
Name: |
dwc_lpddr54_phy_tsmc7ff18 |
Version: |
3.20a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
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Subscribe for Notifications |
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Application Notes DesignWare Cores LPDDR5/4/4X PHY IBIS Model Application Note (Version 1.41a) ( PDF | HTML )
DesignWare Cores LPDDR5/4 PHY OCC Implementation Using Internal PLL Application Note (Version:1.10a) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY ATE Firmware Application Note (FW Version: C-2021.10) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY CTB and Verification Application Note (CTB Version: C-2021-10) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY Diagnostics Firmware Application Note (FW Version: C-2021.10) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY Interconnect Signal and Power Integrity Guidelines Version 1.20a ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY PHYInit Software Overview Application Note ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY Quickboot Application Note (Version C-2021.10) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY Training Firmware Application Note (FW Version: C-2021.10) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY coreKit User Guide (coreKit Version:2.20a) ( PDF | HTML )
Databooks DesignWare Cores LPDDR5/4/4x PHY Databook for TSMC7FF18 (PHY Version: 3.20a) ( PDF | HTML )
Synopsys PHY IP LPDDR5/4/4X PHY Utility Block Databook (PUB Version: 2.20a_d4) ( PDF | HTML )
Implementation Guide Synopsys PHY IP LPDDR5/4/4X PHY Implementation Guide (Doc. Version 2.80a) ( PDF | HTML )
Release Notes DesignWare Cores LPDDR5/4/4x PHY Release Notes (PHY Version: 3.20a) ( TEXT )
|
Download: |
dwc_lpddr54_phy_tsmc7ff18 |
Product Code: |
D221-0 |
Description: |
LPDDR5/4/4X PHY - TSMC N7 for Automotive, ASIL B Random, AEC-Q100 Grade 2 |
Name: |
dwc_ap_lpddr54_phy_tsmc7ff18 |
Version: |
2.50a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
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Application Notes DesignWare Cores LPDDR5/4/4X PHY IBIS Model Application Note (Version 1.51a_d1) ( PDF | HTML )
DesignWare Cores LPDDR5/4 PHY OCC Implementation Using Internal PLL Application Note (Version:1.10a) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY ATE Firmware Application Note (FW Version: C-2022.10)) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY CTB and Verification Application Note (CTB Version: C-2022-10) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY Diagnostics Firmware Application Note (FW Version: C-2022.10) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY Interconnect Signal and Power Integrity Guidelines Version 1.20a ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY PHYInit Software Overview Application Note ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY Quickboot Application Note (Version C-2022.10) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY Training Firmware Application Note (FW Version: C-2022.10) ( PDF | HTML )
Databooks DesignWare Cores LPDDR5/4/4x PHY Databook for Automotive Package Grade 2 (AP) TSMC7FF18 (PHY Version: 2.50a) ( PDF | HTML )
DesignWare Cores LPDDR5/4/4X PHY Utility Block Databook (PUB Version: 1.02a_patch3, December 7, 2022) ( PDF | HTML )
Implementation Guide Synopsys PHY IP LPDDR5/4/4X PHY Implementation Guide (Doc. Version 2.80a) ( PDF | HTML )
Reference Manual DesignWare Cores LPDDR5/4/4x PHY Reliability Report for Automotive Grade 2 (AP) TSMC7FFC18 (Doc. Version: 1.00a) ( PDF )
Release Notes DesignWare Cores LPDDR5/4/4x PHY Release Notes for Automotive Package Grade 2 (AP) TSMC7FF18 (PHY Version: 2.50a) ( TEXT )
|
Download: |
dwc_ap_lpddr54_phy_tsmc7ff18 |
Product Code: |
D771-0 |