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ORCID26th FPGA 2018: Monterey, CA, USA
- Jason Helge Anderson, Kia Bazargan:
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2018, Monterey, CA, USA, February 25-27, 2018. ACM 2018
Special Session: Deep Learning
- Bita Darvish Rouhani, Mohammad Ghasemzadeh, Farinaz Koushanfar
:
CausaLearn: Automated Framework for Scalable Streaming-based Causal Bayesian Learning using FPGAs. 1-10 - Shuo Wang, Zhe Li, Caiwen Ding, Bo Yuan, Qinru Qiu, Yanzhi Wang, Yun Liang:
C-LSTM: Enabling Efficient LSTM using Structured Compression Techniques on FPGAs. 11-20 - Chang Gao, Daniel Neil, Enea Ceolini, Shih-Chii Liu, Tobi Delbrück:
DeltaRNN: A Power-efficient Recurrent Neural Network Accelerator. 21-30 - Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Shimpei Sato:
A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA. 31-40
Session 1: Architecture
- Stephen M. Williams, Mingjie Lin:
Architecture and Circuit Design of an All-Spintronic FPGA. 41-50 - Yue Zha, Jing Li:
Liquid Silicon: A Data-Centric Reconfigurable Architecture Enabled by RRAM Technology. 51-60 - Wenyi Feng, Jonathan W. Greene, Alan Mishchenko:
Improving FPGA Performance with a S44 LUT Structure. 61-66
Session 2: CAD
- Chin Hau Hoo, Akash Kumar:
ParaDRo: A Parallel Deterministic Router Based on Spatial Partitioning and Scheduling. 67-76 - Soheil Mohajer, Zhiheng Wang, Kia Bazargan:
Routing Magic: Performing Computations Using Routing Networks and Voting Logic on Unary Encoded Data. 77-86 - Shenghsun Cho, Mrunal Patel, Han Chen, Michael Ferdman, Peter A. Milder:
A Full-System VM-HDL Co-Simulation Framework for Servers with PCIe-Connected FPGAs. 87-96
Session 3: Deep Learning
- Junzhong Shen, You Huang, Zelong Wang, Yuran Qiao, Mei Wen, Chunyuan Zhang:
Towards a Uniform Template-based Architecture for Accelerating 2D and 3D CNNs on FPGA. 97-106 - Duncan J. M. Moss, Krishnan Srivatsan, Eriko Nurvitadhi, Piotr Ratuszniak, Chris Johnson, Jaewoong Sim, Asit K. Mishra, Debbie Marr, Suchit Subhaschandra, Philip Heng Wai Leong:
A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study. 107-116 - Hanqing Zeng, Ren Chen, Chi Zhang, Viktor K. Prasanna:
A Framework for Generating High Throughput CNN Implementations on FPGAs. 117-126
Session 4: High Level Synthesis 1
- Lana Josipovic, Radhika Ghosal, Paolo Ienne:
Dynamically Scheduled High-level Synthesis. 127-136 - Steve Dai, Gai Liu, Zhiru Zhang:
A Scalable Approach to Exact Resource-Constrained Scheduling Based on a Joint SDC and SAT Formulation. 137-146 - Jeferson Santiago da Silva, François-Raymond Boyer, J. M. Pierre Langlois:
P4-Compatible High-Level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs. 147-152
Session 5: Applications 1
- Hamid Reza Zohouri, Artur Podobas, Satoshi Matsuoka:
Combined Spatial and Temporal Blocking for High-Performance Stencil Computation on FPGAs Using OpenCL. 153-162 - Jan Dürre, Dario Paradzik, Holger Blume:
A HOG-based Real-time and Multi-scale Pedestrian Detector Demonstration System on FPGA. 163-172 - Greg Stitt, Abhay Gupta, Madison N. Emas, David Wilson, Austin Baylis:
Scalable Window Generation for the Intel Broadwell+Arria 10 and High-Bandwidth FPGA Systems. 173-182 - Martin Langhammer, Bogdan Pasca:
High-Performance QR Decomposition for FPGAs. 183-188
Session 6: High Level Synthesis 2
- Ho-Cheung Ng, Shuanglong Liu, Wayne Luk:
ADAM: Automated Design Analysis and Merging for Speeding up FPGA Development. 189-198 - Juan Escobedo, Mingjie Lin:
Graph-Theoretically Optimal Memory Banking for Stencil-Based Computing Kernels. 199-208 - Al-Shahna Jamal, Jeffrey Goeders, Steven J. E. Wilton:
Architecture Exploration for HLS-Oriented FPGA Debug Overlays. 209-218
Session 7: Circuits and Computation Engines
- François Serre, Markus Püschel:
Memory-Efficient Fast Fourier Transform on Streaming Data by Fusing Permutations. 219-228 - Jialiang Zhang, Jing Li:
Degree-aware Hybrid Graph Traversal on FPGA-HMC Platform. 229-238 - Soroosh Khoram, Jialiang Zhang, Maxwell Strange, Jing Li:
Accelerating Graph Analytics by Co-Optimizing Storage and Access on an FPGA-HMC Platform. 239-248
Session 8: Applications 2
- Jakub Cabal, Pavel Benácek, Lukas Kekely, Michal Kekely, Viktor Pus, Jan Korenek:
Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput. 249-258 - Shijie Zhou, Rajgopal Kannan, Yu Min, Viktor K. Prasanna:
FASTCF: FPGA-based Accelerator for STochastic-Gradient-Descent-based Collaborative Filtering. 259-268 - Yuan Zhou, Udit Gupta, Steve Dai, Ritchie Zhao, Nitish Kumar Srivastava, Hanchen Jin, Joseph Featherston, Yi-Hsiang Lai, Gai Liu, Gustavo Angarita Velasquez, Wenping Wang, Zhiru Zhang:
Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs. 269-278 - Sean Fox, David Boland, Philip Heng Wai Leong:
FPGA Fastfood - A High Speed Systolic Implementation of a Large Scale Online Kernel Method. 279-284
Poster Session 1
- Zheming Jin, Kazutomo Yoshii:
Optimizations of Sequence Alignment on FPGA: A Case Study of Extended Sequence Alignment (Abstact Only). 285 - Ruizhe Zhao, Xinyu Niu, Wayne Luk:
Automatic Optimising CNN with Depthwise Separable Convolution on FPGA: (Abstact Only). 285 - Kenichi Koizumi, Kei Hiraki, Mary Inaba:
Continuous Skyline Computation Accelerator with Parallelizing Dominance Relation Calculations: (Abstract Only). 285 - Nachiket Kapre, Tushar Krishna:
FastTrack: Exploiting Fast FPGA Wiring for Implementing NoC Shortcuts (Abstract Only). 286 - Yuze Chi, Peipei Zhou, Jason Cong:
An Optimal Microarchitecture for Stencil Computation with Data Reuse and Fine-Grained Parallelism: (Abstract Only). 286 - Haiyue Song, Xiang Song, Tianjian Li, Hao Dong, Naifeng Jing, Xiaoyao Liang, Li Jiang:
A FPGA Friendly Approximate Computing Framework with Hybrid Neural Networks: (Abstract Only). 286 - Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Sergey Y. Shumarayev, Aravind Dasu:
In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only). 287 - Zheming Jin, Hal Finkel:
Evaluation of OpenCL Performance-oriented Optimizations for Streaming Kernels on the FPGA: (Abstract Only). 287 - Jason Cong, Zhenman Fang, Yao Hu, Di Wu:
K-Flow: A Programming and Scheduling Framework to Optimize Dataflow Execution on CPU-FPGA Platforms: (Abstract Only). 287 - Zhe Chen, Andrew Howe, Hugh T. Blair, Jason Cong:
FPGA-based LSTM Acceleration for Real-Time EEG Signal Processing: (Abstract Only). 288 - Jason Cong, Zhenman Fang, Michael Lo, Hanrui Wang, Jingxian Xu, Shaochong Zhang:
Understanding Performance Differences of FPGAs and GPUs: (Abtract Only). 288
Poster Session 2
- Nan Ding, Wei Zhang, Yanhua Ma, Zhenguo Gao:
Software/Hardware Co-design for Multichannel Scheduling in IEEE 802.11p MLME: (Abstract Only). 289 - Juexiao Su, Lei He:
Solving Satisfiability Problem on Quantum Annealer: A Lesson from FPGA CAD Tools: (Abstract Only). 289 - Chongchong Xu, Chao Wang, Yiwei Zhang, Lei Gong, Xi Li, Xuehai Zhou:
Domino: An Asynchronous and Energy-efficient Accelerator for Graph Processing: (Abstract Only). 289 - Minghua Shen, Wentai Zhang, Nong Xiao, Guojie Luo:
Towards Serial-Equivalent Parallel Routing for FPGAs: (Abstract Only). 289 - Matej Bartík, Sven Ubik, Pavel Kubalík, Tomás Benes:
Performance Comparison of Multiple Approaches of Status Register for Medium Density Memory Suitable for Implementation of a Lossless Compression Dictionary: (Abstract Only). 290 - Minghua Shen, Jiaxi Zhang, Nong Xiao, Guojie Luo:
BoxPlacer: Force Directed-Based Timing-Driven Placement for Large-Scale FPGAs: (Abstract Only). 290 - Gai Liu, Ecenur Ustun, Shaojie Xiang, Chang Xu, Guojie Luo, Zhiru Zhang:
DATuner: An Extensible Distributed Autotuning Framework for FPGA Design and Design Automation: (Abstract Only). 290 - Wentai Zhang, Jiaxi Zhang, Minghua Shen, Nong Xiao, Guojie Luo:
Mapping Large-Scale DNNs on Asymmetric FPGAs: (Abstract Only). 291 - Yankang Du, Qinrang Liu, Shuai Wei, Chen Gao:
Software-Defined FPGA-Based Accelerator for Deep Convolutional Neural Networks: (Abstract Only). 291 - Daisuke Suzuki, Takahiro Hanyu:
Design of an MTJ-Based Nonvolatile LUT Circuit with a Data-Update Minimized Shift Operation for an Ultra-Low-Power FPGA: (Abstract Only). 291 - Weikang Qiao, Jieqiong Du, Zhenman Fang, Libo Wang, Michael Lo, Mau-Chung Frank Chang, Jason Cong:
High-Throughput Lossless Compression on Tightly Coupled CPU-FPGA Platforms: (Abstract Only). 291
Poster Session 3
- Fady Hussein, Luka Daoud, Nader Rafla:
HexCell: a Hexagonal Cell for Evolvable Systolic Arrays on FPGAs: (Abstract Only). 293 - Xiaoyu Yu, Dong Ye:
Performance Comparison of Multiples and Target Detection with Imager-driven Processing Mode for Ultrafast-Imager: (Abstract Only). 293 - Shuanglong Liu, Xinyu Niu, Wayne Luk:
A Low-Power Deconvolutional Accelerator for Convolutional Neural Network Based Segmentation on FPGA: Abstract Only. 293 - Mikhail Asiatici, Damian Maiorano, Paolo Ienne:
FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort (pHS5)(Abstract Only). 294 - Luka Daoud, Muhammad Kamran Latif, Nader Rafla:
SIFT Keypoint Descriptor Matching Algorithm: A Fully Pipelined Accelerator on FPGA(Abstract Only). 294 - Oluseyi A. Ayorinde, He Qi, Benton H. Calhoun:
FGC: A Tool-flow for Generating and Configuring Custom FPGAs(Abstract Only). 294 - Philip Colangelo, Nasibeh Nasiri, Eriko Nurvitadhi, Asit K. Mishra, Martin Margala, Kevin Nealis:
Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs: (Abstract Only). 294 - Andrea Guerrieri, Sahand Kashani-Akhavan, Mikhail Asiatici, Pasquale Lombardi, Bilel Belhadj, Paolo Ienne:
LEOSoC: An Open-Source Cross-Platform Embedded Linux Library for Managing Hardware Accelerators in Heterogeneous System-on-Chips(Abstract Only). 295 - Ning Mao, Zhihong Huang, Xing Wei, He Zhao, Xinkai Di, Le Yu, Haigang Yang:
A Self-adaptation Method of Fitting Convolutional Neural Network into FPGA: Abstract Only). 295
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