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2020 – today
- 2024
[j23]Courtney Golden
, Dan Ilan, Caroline Huang, Niansong Zhang, Zhiru Zhang, Christopher Batten:
Supporting a Virtual Vector Instruction Set on a Commercial Compute-in-SRAM Accelerator. IEEE Comput. Archit. Lett. 23(1): 29-32 (2024)- [j22]Jie Liu, Zhongyuan Zhao, Zijian Ding, Benjamin Brock, Hongbo Rong, Zhiru Zhang:
UniSparse: An Intermediate Language for General Sparse Format Customization. Proc. ACM Program. Lang. 8(OOPSLA1): 137-165 (2024) - [j21]Hongzheng Chen, Niansong Zhang, Shaojie Xiang, Zhichen Zeng, Mengjia Dai, Zhiru Zhang:
Allo: A Programming Model for Composable Accelerator Design. Proc. ACM Program. Lang. 8(PLDI): 593-620 (2024) - [c114]Hongzheng Chen, Cody Hao Yu, Shuai Zheng, Zhen Zhang, Zhiru Zhang, Yida Wang:
Slapo: A Schedule Language for Progressive Optimization of Large Deep Learning Model Training. ASPLOS (2) 2024: 1095-1111 - [c113]Chenhui Deng, Zichao Yue, Cunxi Yu, Gokce Sarar, Ryan Carey, Rajeev Jain, Zhiru Zhang:
Less is More: Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits. DAC 2024: 175:1-175:6 - [c112]Yash Akhauri, Ahmed F. AbouElhamayed, Jordan Dotzel, Zhiru Zhang, Alexander M. Rush, Safeen Huda, Mohamed S. Abdelfattah:
ShadowLLM: Predictor-based Contextual Sparsity for Large Language Models. EMNLP 2024: 19154-19167 - [c111]Louis-Noël Pouchet, Emily Tucker, Niansong Zhang, Hongzheng Chen, Debjit Pal, Gabriel Rodríguez, Zhiru Zhang:
Formal Verification of Source-to-Source Transformations for HLS. FPGA 2024: 97-107 - [c110]Hongzheng Chen, Jiahao Zhang, Yixiao Du, Shaojie Xiang, Zichao Yue, Niansong Zhang, Yaohui Cai, Zhiru Zhang:
A Comprehensive Evaluation of FPGA-Based Spatial Acceleration of LLMs. FPGA 2024: 185 - [c109]Yueying Li, Nikita Lazarev, David Koufaty, Tenny Yin, Andy Anderson, Zhiru Zhang, G. Edward Suh, Kostis Kaffes, Christina Delimitrou:
LibPreemptible: Enabling Fast, Adaptive, and Hardware-Assisted User-Space Scheduling. HPCA 2024: 922-936 - [c108]Chenhui Deng, Zichao Yue, Zhiru Zhang:
Polynormer: Polynomial-Expressive Graph Transformer in Linear Time. ICLR 2024 - [c107]Jordan Dotzel, Bahaa Kotb, James Dotzel, Mohamed S. Abdelfattah, Zhiru Zhang:
Exploring the Limits of Semantic Image Compression at Micro-bits per Pixel. Tiny Papers @ ICLR 2024 - [c106]Jordan Dotzel, Yuzong Chen, Bahaa Kotb, Sushma Prasad, Gang Wu, Sheng Li, Mohamed S. Abdelfattah, Zhiru Zhang:
Learning from Students: Applying t-Distributions to Explore Accurate and Efficient Formats for LLMs. ICML 2024 - [c105]Mingju Liu, Yingjie Li, Jiaqi Yin, Zhiru Zhang, Cunxi Yu:
Differentiable Combinatorial Scheduling at Scale. ICML 2024 - [c104]Dai Cheol Jung, Max Ruttenberg, Paul Gao, Scott Davidson, Daniel Petrisko, Kangli Li, Aditya K. Kamath, Lin Cheng, Shaolin Xie, Peitian Pan, Zhongyuan Zhao, Zichao Yue, Bandhav Veluri, Sripathi Muralitharan, Adrian Sampson, Andrew Lumsdaine, Zhiru Zhang, Christopher Batten, Mark Oskin, Dustin Richmond, Michael Bedford Taylor:
Scalable, Programmable and Dense: The HammerBlade Open-Source RISC-V Manycore. ISCA 2024: 770-784 - [c103]Nikita Lazarev, Varun Gohil, James Tsai, Andy Anderson, Bhushan Chitlur, Zhiru Zhang, Christina Delimitrou:
Sabre: Hardware-Accelerated Snapshot Compression for Serverless MicroVMs. OSDI 2024: 1-18 - [e2]Zhiru Zhang, Andrew Putnam:
Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2024, Monterey, CA, USA, March 3-5, 2024. ACM 2024 [contents] - [i46]Dingyi Dai, Yichi Zhang, Jiahao Zhang, Zhanqiu Hu, Yaohui Cai, Qi Sun, Zhiru Zhang:
Trainable Fixed-Point Quantization for Deep Learning Acceleration on FPGAs. CoRR abs/2401.17544 (2024) - [i45]Wuxinlin Cheng, Chenhui Deng, Ali Aghdaei, Zhiru Zhang, Zhuo Feng:
SAGMAN: Stability Analysis of Graph Neural Networks on the Manifolds. CoRR abs/2402.08653 (2024) - [i44]Jordan Dotzel, Bahaa Kotb, James Dotzel, Mohamed S. Abdelfattah, Zhiru Zhang:
Exploring the Limits of Semantic Image Compression at Micro-bits per Pixel. CoRR abs/2402.13536 (2024) - [i43]Chenhui Deng, Zichao Yue, Zhiru Zhang:
Polynormer: Polynomial-Expressive Graph Transformer in Linear Time. CoRR abs/2403.01232 (2024) - [i42]Chenhui Deng, Zichao Yue, Cunxi Yu, Gokce Sarar, Ryan Carey, Rajeev Jain, Zhiru Zhang:
Less is More: Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits. CoRR abs/2403.01317 (2024) - [i41]Jie Liu, Zhongyuan Zhao, Zijian Ding, Benjamin Brock, Hongbo Rong, Zhiru Zhang:
UniSparse: An Intermediate Language for General Sparse Format Customization. CoRR abs/2403.05802 (2024) - [i40]Hongzheng Chen, Niansong Zhang, Shaojie Xiang, Zhichen Zeng, Mengjia Dai, Zhiru Zhang:
Allo: A Programming Model for Composable Accelerator Design. CoRR abs/2404.04815 (2024) - [i39]Jordan Dotzel, Yash Akhauri, Ahmed S. AbouElhamayed, Carly Jiang, Mohamed S. Abdelfattah, Zhiru Zhang:
Radial Networks: Dynamic Layer Routing for High-Performance Large Language Models. CoRR abs/2404.04900 (2024) - [i38]Jordan Dotzel, Yuzong Chen, Bahaa Kotb, Sushma Prasad, Gang Wu, Sheng Li, Mohamed S. Abdelfattah, Zhiru Zhang:
Learning from Students: Applying t-Distributions to Explore Accurate and Efficient Formats for LLMs. CoRR abs/2405.03103 (2024) - [i37]Mingju Liu, Yingjie Li, Jiaqi Yin, Zhiru Zhang, Cunxi Yu:
Differentiable Combinatorial Scheduling at Scale. CoRR abs/2406.06593 (2024) - [i36]Yash Akhauri, Ahmed F. AbouElhamayed, Jordan Dotzel, Zhiru Zhang, Alexander M. Rush, Safeen Huda, Mohamed S. Abdelfattah:
ShadowLLM: Predictor-based Contextual Sparsity for Large Language Models. CoRR abs/2406.16635 (2024) - [i35]Jiajie Li, Jan-Niklas Schmelzle, Yixiao Du, Simon Heumos, Andrea Guarracino, Giulia Guidi, Pjotr Prins, Erik Garrison, Zhiru Zhang:
Rapid GPU-Based Pangenome Graph Layout. CoRR abs/2409.00876 (2024) - 2023
- [j20]Shreyas Kolala Venkataramanaiah, Jian Meng, Han-Sok Suh, Injune Yeo, Jyotishman Saikia, Sai Kiran Cherupally, Yichi Zhang, Zhiru Zhang, Jae-Sun Seo:
A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity. IEEE J. Solid State Circuits 58(7): 1885-1897 (2023) - [j19]Licheng Guo, Pongstorn Maidee, Yun Zhou, Chris Lavin, Eddie Hung, Wuxi Li, Jason Lau, Weikang Qiao, Yuze Chi, Linghao Song, Yuanlong Xiao, Alireza Kaviani, Zhiru Zhang, Jason Cong:
RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration. ACM Trans. Reconfigurable Technol. Syst. 16(4): 59:1-59:30 (2023) - [j18]Licheng Guo, Yuze Chi, Jason Lau, Linghao Song, Xingyu Tian, Moazin Khatti, Weikang Qiao, Jie Wang, Ecenur Ustun, Zhenman Fang, Zhiru Zhang, Jason Cong:
TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design. ACM Trans. Reconfigurable Technol. Syst. 16(4): 63:1-63:31 (2023) - [c102]Erika S. Alcorta, Andreas Gerstlauer, Chenhui Deng, Qi Sun, Zhiru Zhang, Ceyu Xu, Lisa Wu Wills, Daniela Sanchez Lopera, Wolfgang Ecker, Siddharth Garg, Jiang Hu:
Special Session: Machine Learning for Embedded System Design. CODES+ISSS 2023: 28-37 - [c101]Ecenur Ustun, Cunxi Yu, Zhiru Zhang:
Equality Saturation for Datapath Synthesis: A Pathway to Pareto Optimality. DAC 2023: 1-2 - [c100]Zhiru Zhang, Matthew Hofmann, Andrew Butt:
A Case for Open EDA Verticals. ISPD 2023: 208-209 - [c99]Yichi Zhang, Ankush Garg, Yuan Cao, Lukasz Lew, Behrooz Ghorbani, Zhiru Zhang, Orhan Firat:
Binarized Neural Machine Translation. NeurIPS 2023 - [c98]Nikita Lazarev, Tao Ji, Anuj Kalia, Daehyeok Kim, Ilias Marinos, Francis Y. Yan, Christina Delimitrou, Zhiru Zhang, Aditya Akella:
Resilient Baseband Processing in Virtualized RANs with Slingshot. SIGCOMM 2023: 654-667 - [e1]Paolo Ienne, Zhiru Zhang:
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2023, Monterey, CA, USA, February 12-14, 2023. ACM 2023, ISBN 978-1-4503-9417-8 [contents] - [i34]Yichi Zhang, Ankush Garg, Yuan Cao, Lukasz Lew, Behrooz Ghorbani, Zhiru Zhang, Orhan Firat:
Binarized Neural Machine Translation. CoRR abs/2302.04907 (2023) - [i33]Hongzheng Chen, Cody Hao Yu, Shuai Zheng, Zhen Zhang, Zhiru Zhang, Yida Wang:
Decoupled Model Schedule for Deep Learning Training. CoRR abs/2302.08005 (2023) - [i32]Yueying Li, Nikita Lazarev, David Koufaty, Yijun Yin, Andy Anderson, Zhiru Zhang, G. Edward Suh, Kostis Kaffes, Christina Delimitrou:
Towards Fast, Adaptive, and Hardware-Assisted User-Space Scheduling. CoRR abs/2308.02896 (2023) - [i31]Jordan Dotzel, Gang Wu, Andrew Li, Muhammad Umar, Yun Ni, Mohamed S. Abdelfattah, Zhiru Zhang, Liqun Cheng, Martin G. Dixon, Norman P. Jouppi, Quoc V. Le, Sheng Li:
FLIQS: One-Shot Mixed-Precision Floating-Point and Integer Quantization Search. CoRR abs/2308.03290 (2023) - [i30]Ruirong Huang, Zichao Yue, Caroline Huang, Janarbek Matai, Zhiru Zhang:
Comprehensive Benchmarking of Binary Neural Networks on NVM Crossbar Architectures. CoRR abs/2308.06227 (2023) - [i29]Hongzheng Chen, Jiahao Zhang, Yixiao Du, Shaojie Xiang, Zichao Yue, Niansong Zhang, Yaohui Cai, Zhiru Zhang:
Understanding the Potential of FPGA-Based Spatial Acceleration for Large Language Model Inference. CoRR abs/2312.15159 (2023) - 2022
- [j17]Weizhe Hua, Zhiru Zhang, G. Edward Suh:
Reverse-Engineering CNN Models Using Side-Channel Attacks. IEEE Des. Test 39(4): 15-22 (2022) - [j16]Lin Cheng, Peitian Pan, Zhongyuan Zhao, Krithik Ranjan, Jack Weber, Bandhav Veluri, Seyed Borna Ehsani, Max Ruttenberg, Dai Cheol Jung, Preslav Ivanov, Dustin Richmond, Michael B. Taylor, Zhiru Zhang, Christopher Batten:
A Tensor Processing Framework for CPU-Manycore Heterogeneous Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(6): 1620-1635 (2022) - [j15]Jason Cong, Jason Lau, Gai Liu, Stephen Neuendorffer, Peichen Pan, Kees A. Vissers, Zhiru Zhang:
FPGA HLS Today: Successes, Challenges, and Opportunities. ACM Trans. Reconfigurable Technol. Syst. 15(4): 51:1-51:42 (2022) - [c97]Yichi Zhang, Zhiru Zhang, Lukasz Lew:
PokeBNN: A Binary Pursuit of Lightweight Accuracy. CVPR 2022: 12465-12475 - [c96]Weizhe Hua, Muhammad Umar, Zhiru Zhang, G. Edward Suh:
GuardNN: secure accelerator architecture for privacy-preserving deep learning. DAC 2022: 349-354 - [c95]Debjit Pal, Yi-Hsiang Lai, Shaojie Xiang, Niansong Zhang, Hongzheng Chen, Jeremy Casas, Pasquale Cocchini, Zhenkun Yang, Jin Yang, Louis-Noël Pouchet, Zhiru Zhang:
Accelerator design with decoupled hardware customizations: benefits and challenges: invited. DAC 2022: 1351-1354 - [c94]Shreyas Kolala Venkataramanaiah, Jian Meng, Han-Sok Suh, Injune Yeo, Jyotishman Saikia, Sai Kiran Cherupally, Yichi Zhang, Zhiru Zhang, Jae-sun Seo:
A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation/Weight Sparsification. ESSCIRC 2022: 89-92 - [c93]Ecenur Ustun, Ismail San, Jiaqi Yin, Cunxi Yu, Zhiru Zhang:
IMpress: Large Integer Multiplication Expression Rewriting for FPGA HLS. FCCM 2022: 1-10 - [c92]Licheng Guo, Pongstorn Maidee, Yun Zhou, Chris Lavin, Jie Wang, Yuze Chi, Weikang Qiao, Alireza Kaviani, Zhiru Zhang, Jason Cong:
RapidStream: Parallel Physical Implementation of FPGA HLS Designs. FPGA 2022: 1-12 - [c91]Yixiao Du, Yuwei Hu, Zhongchun Zhou, Zhiru Zhang:
High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS: A Case Study on SpMV. FPGA 2022: 54-64 - [c90]Shaojie Xiang, Yi-Hsiang Lai, Yuan Zhou, Hongzheng Chen, Niansong Zhang, Debjit Pal, Zhiru Zhang:
HeteroFlow: An Accelerator Programming Model with Decoupled Data Placement for Software-Defined FPGAs. FPGA 2022: 78-88 - [c89]Jiaqi Yin, Zhiru Zhang, Cunxi Yu:
Exact Memory- and Communication-aware Scheduling of DNNs on Pipelined Edge TPUs. SEC 2022: 203-215 - [c88]Muhammad Umar, Weizhe Hua, Zhiru Zhang, G. Edward Suh:
SoftVN: efficient memory protection via software-provided version numbers. ISCA 2022: 160-172 - [c87]Weizhe Hua, Muhammad Umar, Zhiru Zhang, G. Edward Suh:
MGX: near-zero overhead memory protection for data-intensive accelerators. ISCA 2022: 726-741 - [c86]Chenhui Deng, Xiuyu Li, Zhuo Feng, Zhiru Zhang:
GARNET: Reduced-Rank Topology Learning for Robust and Scalable Graph Neural Networks. LoG 2022: 3 - [c85]Tao Yu, Yichi Zhang, Zhiru Zhang, Christopher De Sa:
Understanding Hyperdimensional Computing for Parallel Single-Pass Learning. NeurIPS 2022 - [i28]Chenhui Deng, Xiuyu Li, Zhuo Feng, Zhiru Zhang:
GARNET: Reduced-Rank Topology Learning for Robust and Scalable Graph Neural Networks. CoRR abs/2201.12741 (2022) - [i27]Tao Yu, Yichi Zhang, Zhiru Zhang, Christopher De Sa:
Understanding Hyperdimensional Computing for Parallel Single-Pass Learning. CoRR abs/2202.04805 (2022) - [i26]Yaohui Cai, Weizhe Hua, Hongzheng Chen, G. Edward Suh, Christopher De Sa, Zhiru Zhang:
Structured Pruning is All You Need for Pruning CNNs at Initialization. CoRR abs/2203.02549 (2022) - [i25]Yuwei Hu, Jiajie Li, Zhongming Yu, Zhiru Zhang:
Benchmarking GNN-Based Recommender Systems on Intel Optane Persistent Memory. CoRR abs/2207.11918 (2022) - [i24]Licheng Guo, Yuze Chi, Jason Lau, Linghao Song, Xingyu Tian, Moazin Khatti, Weikang Qiao, Jie Wang, Ecenur Ustun, Zhenman Fang, Zhiru Zhang, Jason Cong:
TAPA: A Scalable Task-Parallel Dataflow Programming Framework for Modern FPGAs with Co-Optimization of HLS and Physical Design. CoRR abs/2209.02663 (2022) - 2021
- [j14]Luca Benini, Deming Chen, Jinjun Xiong, Zhiru Zhang:
Guest Editors' Introduction: Machine Intelligence at the Edge. IEEE Des. Test 38(4): 5-6 (2021) - [j13]Cong Hao, Jordan Dotzel, Jinjun Xiong, Luca Benini, Zhiru Zhang, Deming Chen:
Enabling Design Methodologies and Future Trends for Edge AI: Specialization and Codesign. IEEE Des. Test 38(4): 7-26 (2021) - [j12]Yi-Hsiang Lai, Ecenur Ustun, Shaojie Xiang, Zhenman Fang, Hongbo Rong, Zhiru Zhang:
Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future Prospects. ACM Trans. Reconfigurable Technol. Syst. 14(4): 17:1-17:39 (2021) - [c84]Xiaohan Gao, Chenhui Deng, Mingjie Liu, Zhiru Zhang, David Z. Pan, Yibo Lin:
Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks. ASP-DAC 2021: 152-157 - [c83]Nikita Lazarev, Shaojie Xiang, Neil Adit, Zhiru Zhang, Christina Delimitrou:
Dagger: efficient and fast RPCs in cloud microservices with near-memory reconfigurable NICs. ASPLOS 2021: 36-51 - [c82]Yuan Zhou, Hanyu Wang, Jieming Yin, Zhiru Zhang:
Distilling Arbitration Logic from Traces using Machine Learning: A Case Study on NoC. DAC 2021: 55-60 - [c81]Jiajia Jiao, Debjit Pal, Chenhui Deng, Zhiru Zhang:
GLAIVE: Graph Learning Assisted Instruction Vulnerability Estimation. DATE 2021: 82-87 - [c80]Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee:
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. DATE 2021: 1026-1031 - [c79]Saranyu Chattopadhyay, Florian Lonsing, Luca Piccolboni, Deepraj Soni, Peng Wei, Xiaofan Zhang, Yuan Zhou, Luca P. Carloni, Deming Chen, Jason Cong, Ramesh Karri, Zhiru Zhang, Caroline Trippel, Clark W. Barrett, Subhasish Mitra:
Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition. FMCAD 2021: 42-52 - [c78]Licheng Guo, Yuze Chi, Jie Wang, Jason Lau, Weikang Qiao, Ecenur Ustun, Zhiru Zhang, Jason Cong:
AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs. FPGA 2021: 81-92 - [c77]Yichi Zhang, Junhao Pan, Xinheng Liu, Hongzheng Chen, Deming Chen, Zhiru Zhang:
FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations. FPGA 2021: 171-182 - [c76]Yuwei Hu, Yixiao Du, Ecenur Ustun, Zhiru Zhang:
GraphLily: Accelerating Graph Linear Algebra on HBM-Equipped FPGAs. ICCAD 2021: 1-9 - [c75]Wuxinlin Cheng, Chenhui Deng, Zhiqiang Zhao, Yaohui Cai, Zhiru Zhang, Zhuo Feng:
SPADE: A Spectral Method for Black-Box Adversarial Robustness Evaluation. ICML 2021: 1814-1824 - [c74]Weizhe Hua, Yichi Zhang, Chuan Guo, Zhiru Zhang, G. Edward Suh:
BulletTrain: Accelerating Robust Neural Network Training via Boundary Example Mining. NeurIPS 2021: 18527-18538 - [i23]Wuxinlin Cheng, Chenhui Deng, Zhiqiang Zhao, Yaohui Cai, Zhiru Zhang, Zhuo Feng:
SPADE: A Spectral Method for Black-Box Adversarial Robustness Evaluation. CoRR abs/2102.03716 (2021) - [i22]Cong Hao, Jordan Dotzel, Jinjun Xiong, Luca Benini, Zhiru Zhang, Deming Chen:
Enabling Design Methodologies and Future Trends for Edge AI: Specialization and Co-design. CoRR abs/2103.15750 (2021) - [i21]Nikita Lazarev, Shaojie Xiang, Neil Adit, Zhiru Zhang, Christina Delimitrou:
Dagger: Accelerating RPCs in Cloud Microservices Through Tightly-Coupled Reconfigurable NICs. CoRR abs/2106.01482 (2021) - [i20]Saranyu Chattopadhyay, Florian Lonsing, Luca Piccolboni, Deepraj Soni, Peng Wei, Xiaofan Zhang, Yuan Zhou, Luca P. Carloni, Deming Chen, Jason Cong, Ramesh Karri, Zhiru Zhang, Caroline Trippel, Clark W. Barrett, Subhasish Mitra:
Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition. CoRR abs/2108.06081 (2021) - [i19]Mark Buckler, Neil Adit, Yuwei Hu, Zhiru Zhang, Adrian Sampson:
Dense Pruning of Pointwise Convolutions in the Frequency Domain. CoRR abs/2109.07707 (2021) - [i18]Weizhe Hua, Yichi Zhang, Chuan Guo, Zhiru Zhang, G. Edward Suh:
BulletTrain: Accelerating Robust Neural Network Training via Boundary Example Mining. CoRR abs/2109.14707 (2021) - [i17]Daehyeok Kim, Nikita Lazarev, Tommy Tracy II, Farzana Siddique, Hun Namkung, James C. Hoe, Vyas Sekar, Kevin Skadron, Zhiru Zhang, Srinivasan Seshan:
A Roadmap for Enabling a Future-Proof In-Network Computing Data Plane Ecosystem. CoRR abs/2111.04563 (2021) - [i16]Yichi Zhang, Zhiru Zhang, Lukasz Lew:
PokeBNN: A Binary Pursuit of Lightweight Accuracy. CoRR abs/2112.00133 (2021) - 2020
- [j11]Nikita Lazarev, Neil Adit, Shaojie Xiang, Zhiru Zhang, Christina Delimitrou:
Dagger: Towards Efficient RPCs in Cloud Microservices With Near-Memory Reconfigurable NICs. IEEE Comput. Archit. Lett. 19(2): 134-138 (2020) - [c73]Licheng Guo, Jason Lau, Yuze Chi, Jie Wang, Cody Hao Yu, Zhe Chen, Zhiru Zhang, Jason Cong:
Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency. DAC 2020: 1-6 - [c72]Eshan Singh, Florian Lonsing, Saranyu Chattopadhyay, Maxwell Strange, Peng Wei, Xiaofan Zhang, Yuan Zhou, Deming Chen, Jason Cong, Priyanka Raina, Zhiru Zhang, Clark W. Barrett, Subhasish Mitra:
A-QED Verification of Hardware Accelerators. DAC 2020: 1-6 - [c71]Licheng Guo, Jason Lau, Yuze Chi, Jie Wang, Cody Hao Yu, Zhe Chen, Zhiru Zhang, Jason Cong:
Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency. FPGA 2020: 311 - [c70]Nitish Kumar Srivastava, Hanchen Jin, Shaden Smith, Hongbo Rong, David H. Albonesi, Zhiru Zhang:
Tensaurus: A Versatile Accelerator for Mixed Sparse-Dense Tensor Computations. HPCA 2020: 689-702 - [c69]Yi-Hsiang Lai, Hongbo Rong, Size Zheng, Weihao Zhang, Xiuping Cui, Yunshan Jia, Jie Wang, Brendan Sullivan, Zhiru Zhang, Yun Liang, Youhui Zhang, Jason Cong, Nithin George, Jose Alvarez, Christopher J. Hughes, Pradeep Dubey:
SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs. ICCAD 2020: 73:1-73:9 - [c68]Ecenur Ustun, Chenhui Deng, Debjit Pal, Zhijing Li, Zhiru Zhang:
Accurate Operation Delay Prediction for FPGA HLS Using Graph Neural Networks. ICCAD 2020: 87:1-87:9 - [c67]Chenhui Deng, Zhiqiang Zhao, Yongyu Wang, Zhiru Zhang, Zhuo Feng:
GraphZoom: A Multi-level Spectral Approach for Accurate and Scalable Graph Embedding. ICLR 2020 - [c66]Yichi Zhang, Ritchie Zhao, Weizhe Hua, Nayun Xu, G. Edward Suh, Zhiru Zhang:
Precision Gating: Improving Neural Network Efficiency with Dynamic Dual-Precision Activations. ICLR 2020 - [c65]Nitish Kumar Srivastava, Hanchen Jin, Jie Liu, David H. Albonesi, Zhiru Zhang:
MatRaptor: A Sparse-Sparse Matrix Multiplication Accelerator Based on Row-Wise Product. MICRO 2020: 766-780 - [c64]Rachit Nigam, Sachille Atapattu, Samuel Thomas, Zhijing Li, Theodore Bauer, Yuwei Ye, Apurva Koti, Adrian Sampson, Zhiru Zhang:
Predictable accelerator design with time-sensitive affine types. PLDI 2020: 393-407 - [c63]Yuwei Hu, Zihao Ye, Minjie Wang, Jiali Yu, Da Zheng, Mu Li, Zheng Zhang, Zhiru Zhang, Yida Wang:
FeatGraph: a flexible and efficient backend for graph neural network systems. SC 2020: 71 - [i15]Yichi Zhang, Ritchie Zhao, Weizhe Hua, Nayun Xu, G. Edward Suh, Zhiru Zhang:
Precision Gating: Improving Neural Network Efficiency with Dynamic Dual-Precision Activations. CoRR abs/2002.07136 (2020) - [i14]Rachit Nigam, Sachille Atapattu, Samuel Thomas, Zhijing Li, Theodore Bauer, Yuwei Ye, Apurva Koti, Adrian Sampson, Zhiru Zhang:
Predictable Accelerator Design with Time-Sensitive Affine Types. CoRR abs/2004.04852 (2020) - [i13]Weizhe Hua, Muhammad Umar, Zhiru Zhang, G. Edward Suh:
MgX: Near-Zero Overhead Memory Protection with an Application to Secure DNN Acceleration. CoRR abs/2004.09679 (2020) - [i12]Nikita Lazarev, Neil Adit, Shaojie Xiang, Zhiru Zhang, Christina Delimitrou:
Dagger: Towards Efficient RPCs in Cloud Microservices with Near-Memory Reconfigurable NICs. CoRR abs/2007.08622 (2020) - [i11]Yuwei Hu, Zihao Ye, Minjie Wang, Jiali Yu, Da Zheng, Mu Li, Zheng Zhang, Zhiru Zhang, Yida Wang:
FeatGraph: A Flexible and Efficient Backend for Graph Neural Network Systems. CoRR abs/2008.11359 (2020) - [i10]Weizhe Hua, Muhammad Umar, Zhiru Zhang, G. Edward Suh:
GuardNN: Secure DNN Accelerator for Privacy-Preserving Deep Learning. CoRR abs/2008.11632 (2020) - [i9]Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa Jr., Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee:
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. CoRR abs/2012.02530 (2020) - [i8]Yichi Zhang, Junhao Pan, Xinheng Liu, Hongzheng Chen, Deming Chen, Zhiru Zhang:
FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations. CoRR abs/2012.12206 (2020)
2010 – 2019
- 2019
- [j10]Gai Liu, Zhiru Zhang:
PIMap: A Flexible Framework for Improving LUT-Based Technology Mapping via Parallelized Iterative Optimization. ACM Trans. Reconfigurable Technol. Syst. 11(4): 23:1-23:23 (2019) - [c62]Ritchie Zhao, Yuwei Hu, Jordan Dotzel, Christopher De Sa, Zhiru Zhang:
Building Efficient Deep Neural Networks With Unitary Group Convolutions. CVPR 2019: 11303-11312 - [c61]Yuan Zhou, Haoxing Ren, Yanqing Zhang, Ben Keller, Brucek Khailany, Zhiru Zhang:
PRIMAL: Power Inference using Machine Learning. DAC 2019: 39 - [c60]Zhenghong Jiang, Hanchen Jin, G. Edward Suh, Zhiru Zhang:
Designing Secure Cryptographic Accelerators with Information Flow Enforcement: A Case Study on AES. DAC 2019: 59 - [c59]Gai Liu, Joseph Primmer, Zhiru Zhang:
Rapid Generation of High-Qality RISC-V Processors from Functional Instruction Set Specifications. DAC 2019: 122 - [c58]Steve Dai, Zhiru Zhang:
Improving Scalability of Exact Modulo Scheduling with Specialized Conflict-Driven Learning. DAC 2019: 127 - [c57]Cunxi Yu, Zhiru Zhang:
Painting on Placement: Forecasting Routing Congestion using Conditional Generative Adversarial Nets. DAC 2019: 219 - [c56]Ecenur Ustun, Shaojie Xiang, Jinny Gui, Cunxi Yu, Zhiru Zhang:
LAMDA: Learning-Assisted Multi-stage Autotuning for FPGA Design Closure. FCCM 2019: 74-77 - [c55]Nitish Kumar Srivastava, Hongbo Rong, Prithayan Barua, Guanyu Feng, Huanqi Cao, Zhiru Zhang, David H. Albonesi, Vivek Sarkar, Wenguang Chen, Paul Petersen, Geoff Lowney, Adam Herr, Christopher J. Hughes, Timothy G. Mattson, Pradeep Dubey:
T2S-Tensor: Productively Generating High-Performance Spatial Hardware for Dense Tensor Computations. FCCM 2019: 181-189 - [c54]Yi-Hsiang Lai, Yuze Chi, Yuwei Hu, Jie Wang, Cody Hao Yu, Yuan Zhou, Jason Cong, Zhiru Zhang:
HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing. FPGA 2019: 242-251 - [c53]Ritchie Zhao, Yuwei Hu, Jordan Dotzel, Christopher De Sa, Zhiru Zhang:
Improving Neural Network Quantization without Retraining using Outlier Channel Splitting. ICML 2019: 7543-7552 - [c52]Weizhe Hua, Yuan Zhou, Christopher De Sa, Zhiru Zhang, G. Edward Suh:
Boosting the Performance of CNN Accelerators with Dynamic Fine-Grained Channel Gating. MICRO 2019: 139-150 - [c51]Weizhe Hua, Yuan Zhou, Christopher De Sa, Zhiru Zhang, G. Edward Suh:
Channel Gating Neural Networks. NeurIPS 2019: 1884-1894 - [c50]Austin Rovinski, Chun Zhao, Khalid Al-Hawaj, Paul Gao, Shaolin Xie, Christopher Torng, Scott Davidson, Aporva Amarnath, Luis Vega, Bandhav Veluri, Anuj Rao, Tutu Ajayi, Julian Puscar, Steve Dai, Ritchie Zhao, Dustin Richmond, Zhiru Zhang, Ian Galton, Christopher Batten, Michael B. Taylor, Ronald G. Dreslinski:
A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS. VLSI Circuits 2019: 30- - [i7]Ritchie Zhao, Yuwei Hu, Jordan Dotzel, Christopher De Sa, Zhiru Zhang:
Improving Neural Network Quantization without Retraining using Outlier Channel Splitting. CoRR abs/1901.09504 (2019) - [i6]Cunxi Yu, Zhiru Zhang:
Painting on Placement: Forecasting Routing Congestion using Conditional Generative Adversarial Nets. CoRR abs/1904.07077 (2019) - [i5]Chenhui Deng, Zhiqiang Zhao, Yongyu Wang, Zhiru Zhang, Zhuo Feng:
GraphZoom: A multi-level spectral approach for accurate and scalable graph embedding. CoRR abs/1910.02370 (2019) - [i4]Ritchie Zhao, Christopher De Sa, Zhiru Zhang:
Overwrite Quantization: Opportunistic Outlier Handling for Neural Network Accelerators. CoRR abs/1910.06909 (2019) - 2018
- [j9]Scott Davidson, Shaolin Xie, Christopher Torng, Khalid Al-Hawaj, Austin Rovinski, Tutu Ajayi, Luis Vega, Chun Zhao, Ritchie Zhao, Steve Dai, Aporva Amarnath, Bandhav Veluri, Paul Gao, Anuj Rao, Gai Liu, Rajesh K. Gupta, Zhiru Zhang, Ronald G. Dreslinski, Christopher Batten, Michael B. Taylor:
The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips. IEEE Micro 38(2): 30-41 (2018) - [c49]Weizhe Hua, Zhiru Zhang, G. Edward Suh:
Reverse engineering convolutional neural networks through side-channel information leaks. DAC 2018: 4:1-4:6 - [c48]Steve Dai, Yuan Zhou, Hang Zhang, Ecenur Ustun, Evangeline F. Y. Young, Zhiru Zhang:
Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning. FCCM 2018: 129-132 - [c47]Steve Dai, Gai Liu, Zhiru Zhang:
A Scalable Approach to Exact Resource-Constrained Scheduling Based on a Joint SDC and SAT Formulation. FPGA 2018: 137-146 - [c46]Yuan Zhou, Udit Gupta, Steve Dai, Ritchie Zhao, Nitish Kumar Srivastava, Hanchen Jin, Joseph Featherston, Yi-Hsiang Lai, Gai Liu, Gustavo Angarita Velasquez, Wenping Wang, Zhiru Zhang:
Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs. FPGA 2018: 269-278 - [c45]Gai Liu, Ecenur Ustun, Shaojie Xiang, Chang Xu, Guojie Luo, Zhiru Zhang:
DATuner: An Extensible Distributed Autotuning Framework for FPGA Design and Design Automation: (Abstract Only). FPGA 2018: 290 - [c44]Zhenghong Jiang, Steve Dai, G. Edward Suh, Zhiru Zhang:
High-level synthesis with timing-sensitive information flow enforcement. ICCAD 2018: 88 - [i3]Weizhe Hua, Christopher De Sa, Zhiru Zhang, G. Edward Suh:
Channel Gating Neural Networks. CoRR abs/1805.12549 (2018) - [i2]Ritchie Zhao, Yuwei Hu, Jordan Dotzel, Christopher De Sa, Zhiru Zhang:
Building Efficient Deep Neural Networks with Unitary Group Convolutions. CoRR abs/1811.07755 (2018) - 2017
- [j8]Gai Liu, Mingxing Tan, Steve Dai, Ritchie Zhao, Zhiru Zhang:
Architecture and Synthesis for Area-Efficient Pipelining of Irregular Loop Nests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(11): 1817-1830 (2017) - [c43]Steve Dai, Gai Liu, Ritchie Zhao, Zhiru Zhang:
Enabling adaptive loop pipelining in high-level synthesis. ACSSC 2017: 131-135 - [c42]Jeng-Hau Lin, Tianwei Xing, Ritchie Zhao, Zhiru Zhang, Mani B. Srivastava, Zhuowen Tu, Rajesh K. Gupta:
Binarized Convolutional Neural Networks with Separable Filters for Efficient Hardware Acceleration. CVPR Workshops 2017: 344-352 - [c41]Edward Bartz, Jorge Chaves, Yuri Gershtein, Eva Halkiadakis, Michael D. Hildreth, Savvas Kyriacou, Kevin Lannon, Anthony Lefeld, Anders Ryd, Louise Skinnari, Robert Stone, Charles Strohman, Zhengcheng Tao, Brian Winer, Peter Wittich, Zhiru Zhang, Margaret Zientek:
FPGA-Based Real-Time Charged Particle Trajectory Reconstruction at the Large Hadron Collider. FCCM 2017: 64-71 - [c40]Ritchie Zhao, Weinan Song, Wentao Zhang, Tianwei Xing, Jeng-Hau Lin, Mani B. Srivastava, Rajesh Gupta, Zhiru Zhang:
Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs. FPGA 2017: 15-24 - [c39]Gai Liu, Zhiru Zhang:
A Parallelized Iterative Improvement Approach to Area Optimization for LUT-Based Technology Mapping. FPGA 2017: 147-156 - [c38]Chang Xu, Gai Liu, Ritchie Zhao, Stephen Yang, Guojie Luo, Zhiru Zhang:
A Parallel Bandit-Based Approach for Autotuning FPGA Compilation. FPGA 2017: 157-166 - [c37]Yuan Zhou, Khalid Musa Al-Hawaj, Zhiru Zhang:
A New Approach to Automatic Memory Banking using Trace-Based Address Mining. FPGA 2017: 179-188 - [c36]Steve Dai, Ritchie Zhao, Gai Liu, Shreesha Srinath, Udit Gupta, Christopher Batten, Zhiru Zhang:
Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis. FPGA 2017: 189-194 - [c35]Nitish Kumar Srivastava, Steve Dai, Rajit Manohar, Zhiru Zhang:
Accelerating Face Detection on Programmable SoC Using C-Based Synthesis. FPGA 2017: 195-200 - [c34]Gai Liu, Zhiru Zhang:
Statistically certified approximate logic synthesis. ICCAD 2017: 344-351 - [i1]Jeng-Hau Lin, Tianwei Xing, Ritchie Zhao, Zhiru Zhang, Mani B. Srivastava, Zhuowen Tu, Rajesh K. Gupta:
Binarized Convolutional Neural Networks with Separable Filters for Efficient Hardware Acceleration. CoRR abs/1707.04693 (2017) - 2016
- [j7]Deming Chen, Jason Cong, Swathi T. Gurumani, Wen-mei W. Hwu, Kyle Rupnow, Zhiru Zhang:
Platform choices and design demands for IoT platforms: cost, power, and performance tradeoffs. IET Cyper-Phys. Syst.: Theory & Appl. 1(1): 70-77 (2016) - [c33]Ritchie Zhao, Gai Liu, Shreesha Srinath, Christopher Batten, Zhiru Zhang:
Improving high-level synthesis with decoupled data structure optimization. DAC 2016: 137:1-137:6 - [c32]Abhinandan Majumdar, Zhiru Zhang, David H. Albonesi:
Characterizing the Benefits and Limitations of Smart Building Meeting Room Scheduling. ICCPS 2016: 6:1-6:10 - 2015
- [j6]Zhiru Zhang, Deming Chen, Steve Dai, Keith A. Campbell:
High-level Synthesis for Low-power Design. IPSJ Trans. Syst. LSI Des. Methodol. 8: 12-25 (2015) - [c31]Gai Liu, Zhiru Zhang:
A reconfigurable analog substrate for highly efficient maximum flow computation. DAC 2015: 17:1-17:6 - [c30]Ritchie Zhao, Mingxing Tan, Steve Dai, Zhiru Zhang:
Area-efficient pipelining for FPGA-targeted high-level synthesis. DAC 2015: 157:1-157:6 - [c29]Mingxing Tan, Steve Dai, Udit Gupta, Zhiru Zhang:
Mapping-Aware Constrained Scheduling for LUT-Based FPGAs. FPGA 2015: 190-199 - [c28]Mingxing Tan, Gai Liu, Ritchie Zhao, Steve Dai, Zhiru Zhang:
ElasticFlow: A Complexity-Effective Approach for Pipelining Irregular Loop Nests. ICCAD 2015: 78-85 - [c27]Farinaz Koushanfar, Azalia Mirhoseini, Gang Qu, Zhiru Zhang:
DA Systemization of Knowledge: A Catalog of Prior Forward-Looking Initiatives. ICCAD 2015: 255-262 - 2014
- [c26]Steve Dai, Mingxing Tan, Kecheng Hao, Zhiru Zhang:
Flushing-Enabled Loop Pipelining for High-Level Synthesis. DAC 2014: 76:1-76:6 - [c25]Mingxing Tan, Bin Liu, Steve Dai, Zhiru Zhang:
Multithreaded pipeline synthesis for data-parallel kernels. ICCAD 2014: 718-725 - [c24]Gai Liu, Ye Tao, Mingxing Tan, Zhiru Zhang:
CASA: correlation-aware speculative adders. ISLPED 2014: 189-194 - [c23]Shreesha Srinath, Berkin Ilbeyi, Mingxing Tan, Gai Liu, Zhiru Zhang, Christopher Batten:
Architectural Specialization for Inter-Iteration Loop Dependence Patterns. MICRO 2014: 583-595 - 2013
- [c22]Zhiru Zhang, Bin Liu:
SDC-based modulo scheduling for pipeline synthesis. ICCAD 2013: 211-218 - 2012
- [j5]Deming Chen, Kiyoung Choi, Philippe Coussy, Yuan Xie, Zhiru Zhang:
ESL Design Methodology. J. Electr. Comput. Eng. 2012: 358281:1-358281:2 (2012) - 2011
- [j4]Jason Cong, Bin Liu, Stephen Neuendorffer, Juanjo Noguera, Kees A. Vissers, Zhiru Zhang:
High-Level Synthesis for FPGAs: From Prototyping to Deployment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(4): 473-491 (2011) - 2010
- [j3]Jason Cong, Bin Liu, Rupak Majumdar, Zhiru Zhang:
Behavior-Level Observability Analysis for Operation Gating in Low-Power Behavioral Synthesis. ACM Trans. Design Autom. Electr. Syst. 16(1): 4:1-4:29 (2010) - [c21]Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan, Xianhua Liu, Xu Cheng, Jason Cong:
Bit-level optimization for high-level synthesis and FPGA-based acceleration. FPGA 2010: 59-68 - [c20]Fen Chen, Zhiru Zhang, Dongmei Yan:
Image classification with spectral and texture features based on SVM. Geoinformatics 2010: 1-4
2000 – 2009
- 2009
- [c19]Jason Cong, Karthik Gururaj, Bin Liu, Chunyue Liu, Zhiru Zhang, Sheng Zhou, Yi Zou:
Evaluation of Static Analysis Techniques for Fixed-Point Precision Optimization. FCCM 2009: 231-234 - [c18]Jason Cong, Karthik Gururaj, Bin Liu, Chunyue Liu, Yi Zou, Zhiru Zhang, Sheng Zhou:
Revisiting bitwidth optimizations. FPGA 2009: 278 - [c17]Jason Cong, Bin Liu, Zhiru Zhang:
Scheduling with soft constraints. ICCAD 2009: 47-54 - [c16]Jason Cong, Bin Liu, Zhiru Zhang:
Behavior-level observability don't-cares and application to low-power behavioral synthesis. ISLPED 2009: 139-144 - 2008
- [c15]Cheng-Tao Hsieh, Jason Cong, Zhiru Zhang, Shih-Chieh Chang:
Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA. ASP-DAC 2008: 10-15 - [c14]Wei Jiang, Zhiru Zhang, Miodrag Potkonjak, Jason Cong:
Scheduling with integer time budgeting for low-power optimization. ASP-DAC 2008: 22-27 - 2007
- [c13]Deming Chen, Jason Cong, Yiping Fan, Zhiru Zhang:
High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs. ASP-DAC 2007: 529-534 - 2006
- [j2]Jason Cong, Guoling Han, Zhiru Zhang:
Architecture and Compiler Optimizations for Data Bandwidth Improvement in Configurable Processors. IEEE Trans. Very Large Scale Integr. Syst. 14(9): 986-997 (2006) - [c12]Jason Cong, Zhiru Zhang:
An efficient and versatile scheduling algorithm based on SDC formulation. DAC 2006: 433-438 - [c11]Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zhiru Zhang:
Behavior and communication co-optimization for systems with sequential communication media. DAC 2006: 675-678 - [c10]Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zhiru Zhang:
Platform-Based Behavior-Level and System-Level Synthesis. SoCC 2006: 199-202 - 2005
- [c9]Jason Cong, Yiping Fan, Guoling Han, Yizhou Lin, Junjuan Xu, Zhiru Zhang, Xu Cheng:
Bitwidth-aware scheduling and binding in high-level synthesis. ASP-DAC 2005: 856-861 - [c8]Jason Cong, Yiping Fan, Guoling Han, Ashok Jagannathan, Glenn Reinman, Zhiru Zhang:
Instruction set extension with shadow registers for configurable processors. FPGA 2005: 99-106 - [c7]Jason Cong, Guoling Han, Zhiru Zhang:
Architecture and compilation for data bandwidth improvement in configurable embedded processors. ICCAD 2005: 263-270 - 2004
- [j1]Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang:
Architecture and synthesis for on-chip multicycle communication. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(4): 550-564 (2004) - [c6]Jason Cong, Yiping Fan, Zhiru Zhang:
Architecture-level synthesis for automatic interconnect pipelining. DAC 2004: 602-607 - [c5]Jason Cong, Yiping Fan, Guoling Han, Zhiru Zhang:
Application-specific instruction generation for configurable processor architectures. FPGA 2004: 183-189 - 2003
- [c4]Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang:
Architecture and synthesis for multi-cycle on-chip communication. CODES+ISSS 2003: 77-78 - [c3]Zhiru Zhang, Yiping Fan, Miodrag Potkonjak, Jason Cong:
Gradual Relaxation Techniques with Applications to Behavioral Synthesis. ICCAD 2003: 529-535 - [c2]Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang:
Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication. ICCAD 2003: 536-543 - [c1]Jason Cong, Yiping Fan, Xun Yang, Zhiru Zhang:
Architecture and synthesis for multi-cycle communication. ISPD 2003: 190-196
Coauthor Index
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