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ORCID32nd FPL 2022: Belfast, UK
- 32nd International Conference on Field-Programmable Logic and Applications, FPL 2022, Belfast, United Kingdom, August 29 - Sept. 2, 2022. IEEE 2022, ISBN 978-1-6654-7390-3
- Sahand Kashani, Mahyar Emami, James R. Larus:
Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats. 1-8 - Xijie Jia, Yu Zhang, Guangdong Liu, Xinlin Yang, Tianyu Zhang, Jia Zheng, Dongdong Xu, Hong Wang, Rongzhang Zheng, Satyaprakash Pareek, Lu Tian, Dongliang Xie, Hong Luo, Yi Shan:
XVDPU: A High Performance CNN Accelerator on the Versal Platform Powered by the AI Engine. 1-9 - Anqi Guo, Tong Geng, Yongan Zhang, Pouya Haghi, Chunshu Wu, Cheng Tan, Yingyan Lin, Ang Li, Martin C. Herbordt:
A Framework for Neural Network Inference on FPGA-Centric SmartNICs. 1-8 - Bingyi Zhang, Rajgopal Kannan, Viktor K. Prasanna, Carl E. Busart:
Accurate, Low-latency, Efficient SAR Automatic Target Recognition on FPGA. 1-8 - Narasinga Rao Miniskar, Aaron R. Young
, Frank Liu, Willem Blokland, Anthony M. Cabrera, Jeffrey S. Vetter:
Ultra Low Latency Machine Learning for Scientific Edge Applications. 1-7 - Seongyoung Kang, Tarun Sai Ganesh Nerella, Shashank Uppoor, Sang-Woo Jun:
BunchBloomer: Cost-Effective Bloom Filter Accelerator for Genomics Applications. 9-16 - Patrick Plagwitz, Frank Hannig, Jürgen Teich:
TRAC: Compilation-Based Design of Transformer Accelerators for FPGAs. 17-23 - Jonas Dann, Daniel Ritter, Holger Fröning:
GraphScale: Scalable Bandwidth-Efficient Graph Processing on FPGAs. 24-32 - Yehua Ling, Yuanxing Yan, Kai Huang, Gang Chen:
Ultra-Flow: An Ultra-fast and High-quality Optical Flow Accelerator with Deep Feature Matching on FPGA. 33-39 - Andreas Böttcher, Martin Kumm, Florent de Dinechin:
Resource Optimal Squarers for FPGAs. 40-46 - Martha Barker, Stephen A. Edwards, Martha A. Kim:
Synthesized In-BramGarbage Collection for Accelerators with Immutable Memory. 47-53 - Cornelia Wulf, Najdet Charaf, Diana Göhringer:
Virtualization of Reconfigurable Mixed-Criticality Systems. 54-60 - Yunhui Qiu, Yuhang Cao, Yuan Dai, Wenbo Yin, Lingli Wang:
TRAM: An Open-Source Template-based Reconfigurable Architecture Modeling Framework. 61-69 - Yuanlong Xiao, Aditya Hota, Dongjoon Park, André DeHon:
HiPR: High-level Partial Reconfiguration for Fast Incremental FPGA Compilation. 70-78 - Chan-Wei Hu, Jiang Hu, Sunil P. Khatri:
TD3lite: FPGA Acceleration of Reinforcement Learning with Structural and Representation Optimizations. 79-85 - Zhaoteng Meng, Lin Shu, Jie Hao:
A Flexible Real-Time Stereo Vision Architecture for Multiple Data Streams with Runtime Configurable Parameters. 86-93 - Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Jürgen Teich, Stefan Wildermann:
Real-Time Waveform Matching with a Digitizer at 10 GS/s. 94-100 - Chunshu Wu, Sahan Bandara, Tong Geng, Anqi Guo, Pouya Haghi, Vipin Sachdeva, Woody Sherman, Martin C. Herbordt:
Optimized Mappings for Symmetric Range-Limited Molecular Force Calculations on FPGAs. 101-108 - Zhengang Li, Mengshu Sun, Alec Lu, Haoyu Ma, Geng Yuan, Yanyue Xie, Hao Tang, Yanyu Li, Miriam Leeser, Zhangyang Wang, Xue Lin, Zhenman Fang:
Auto-ViT-Acc: An FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization. 109-116 - Clemens Fritzsch, Jörn Hoffmann, Martin Bogdan:
Reduction of Bitstream Size for Low-Cost iCE40 FPGAs. 117-122 - Tianyu Zhang, Dong Li, Hong Wang, Yunzhi Li, Xiang Ma, Wei Luo, Yu Wang, Yang Huang, Yi Li, Yu Zhang, Xinlin Yang, Xijie Jia, Qiang Lin, Lu Tian, Fan Jiang, Dongliang Xie, Hong Luo, Yi Shan:
A-U3D: A Unified 2D/3D CNN Accelerator on the Versal Platform for Disparity Estimation. 123-129 - Ioanna-Maria Panagou, Maria Rafaela Gkeka, Alexandros Patras, Spyros Lalis, Christos D. Antonopoulos, Nikolaos Bellas:
FPGA Roofline modeling and its Application to Visual SLAM. 130-135 - Fan Liu, Sunrui Zhang, Xiaole Cui:
The Design Method of Logic Circuits based on the Voltage-Input Enhanced Scouting Logic Gates. 136-142 - Kohei Ito, Ryota Yasudo, Hideharu Amano:
Optimizing Application Mapping for Multi-FPGA Systems with Multi-ejection STDM Switches. 143-147 - Robert Szafarczyk, Syed Waqar Nabi, Wim Vanderbauwhede:
Reducing FPGA Memory Footprint of Stencil Codes through Automatic Extraction of Memory Patterns. 148-152 - Ariel Podlubne, Johannes Mey, Sergio A. Pertuz, Uwe Aßmann, Diana Göhringer:
Model-based Generation of Hardware/Software Architectures for Robotics Systems. 153-159 - Jan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich:
DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks. 160-166 - Tobias Hahn, Stefan Wildermann, Jürgen Teich:
Auto-Tuning of Raw Filters for FPGAs. 167-175 - Yuan Meng, Rajgopal Kannan, Viktor K. Prasanna:
Accelerating Monte-Carlo Tree Search on CPU-FPGA Heterogeneous Platform. 176-182 - Babar Khan, Carsten Heinz, Andreas Koch:
DeLiBA: An Open-Source Hardware/Software Framework for the Development of Linux Block I/O Accelerators. 183-191 - Chengming Zhang, Tong Geng, Anqi Guo, Jiannan Tian, Martin C. Herbordt, Ang Li, Dingwen Tao:
H-GCN: A Graph Convolutional Network Accelerator on Versal ACAP Architecture. 200-208 - Yashael Faith Arthanto, David Ojika, Joo-Young Kim:
FSHMEM: Supporting Partitioned Global Address Space on FPGAs for Large-Scale Hardware Acceleration Infrastructure. 218-224 - Torben Kalkhof, Andreas Koch:
Direct Device-to-Device Physical Page Migrations in Multi-FPGA Shared Virtual Memory Systems. 225-234 - Ruizhe Zhao, Jianyi Cheng, Wayne Luk, George A. Constantinides:
POLSCA: Polyhedral High-Level Synthesis with Compiler Transformations. 235-242 - Jianyi Cheng, Lana Josipovic, George A. Constantinides, John Wickerson:
Dynamic Inter-Block Scheduling for HLS. 243-252 - Ayatallah Elakhras, Andrea Guerrieri, Lana Josipovic, Paolo Ienne:
Unleashing Parallelism in Elastic Circuits with Faster Token Delivery. 253-261 - Nicolai Fiege, Patrick Sittel, Peter Zipf:
Optimal Binding and Port Assignment for Loop Pipelining in High-Level Synthesis. 262-269 - Stewart Denholm, Wayne Luk:
A Unified Approach for Managing Heterogeneous Processing Elements on FPGAs. 270-276 - Bahar Asgari, Dheeraj Ramchandani, Amaan Marfatia, Hyesoon Kim:
Maia: Matrix Inversion Acceleration Near Memory. 277-281 - Su Zheng, Jiadong Qian, Hao Zhou, Lingli Wang:
GRAEBO: FPGA General Routing Architecture Exploration via Bayesian Optimization. 282-286 - Argyris Kokkinis, Dionysios Diamantopoulos, Kostas Siozios:
Dynamic Heap Management in High-Level Synthesis for Many-Accelerator Architectures. 287-293 - Muhammad A. A. Abdelgawad, Ray C. C. Cheung, Hong Yan:
A High-Performance FPGA Accelerator for CUR Decomposition. 294-299 - Ahmed Kamaleldin, Diana Göhringer:
A Hybrid Memory/Accelerator Tile Architecture for FPGA-based RISC-V Manycore Systems. 300-306 - Yingxue Gao, Lei Gong, Chao Wang, Teng Wang, Xuehai Zhou:
SDMA: An Efficient and Flexible Sparse-Dense Matrix-Multiplication Architecture for GNNs. 307-312 - Peng Zhang, Shijun Zhang, Shang Li, Jin Zhang, Shaoxun Liu, Youjun Bu:
FRA-FPGA: Fast Reconfigurable Automata Processing on FPGAs. 313-321 - Nicolai Fiege, Patrick Sittel, Peter Zipf:
Speeding Up Optimal Modulo Scheduling with Rational Initiation Intervals. 322-326 - Zhiqiang Que, Marcus Loo, Hongxiang Fan, Maurizio Pierini, Alexander D. Tapper, Wayne Luk:
Optimizing Graph Neural Networks for Jet Tagging in Particle Physics on FPGAs. 327-333 - Yee Yang Tan, Felix Staudigl, Lukas Jünger, Anna Drewes, Rainer Leupers, Jan Moritz Joseph:
EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Chip Prototyping on FPGAs. 334-341 - Fanny Spagnolo, Salim Ullah, Pasquale Corsonello, Akash Kumar:
ERMES: Efficient Racetrack Memory Emulation System based on FPGA. 342-349 - Jinjie Ruan, Yisong Chang, Ke Zhang, Kan Shi, Mingyu Chen, Yungang Bao:
Increasing Flexibility of Cloud FPGA Virtualization. 350-357 - Cecilia Latotzke, Tim Ciesielski, Tobias Gemmeke:
Design of High-Throughput Mixed-Precision CNN Accelerators on FPGA. 358-365 - Laurens Le Jeune, Toon Goedemé, Nele Mentens:
Feature dimensionality in CNN acceleration for high-throughput network intrusion detection. 366-374 - Carmine Rizzi, Andrea Guerrieri, Paolo Ienne, Lana Josipovic:
A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits. 375-383 - Bardia Babaei, Dirk Koch:
Tunable Fine-grained Clock Phase-shifting for FPGAs. 384-390 - Christos Diktopoulos, Konstantinos Georgopoulos, Andreas Brokalakis, Georgios Christou, Grigorios Chrysos, Ioannis Morianos, Sotiris Ioannidis:
Assessing the Effectiveness of Active Fences Against SCAs for Multi-Tenant FPGAs. 391-396 - Dennis R. E. Gnad, Jiaqi Hu, Mehdi B. Tahoori:
Breaking an FPGA-Integrated NIST SP 800-193 Compliant TRNG Hard-IP Core with On-Chip Voltage-Based Fault Attacks. 397-403 - Omar Ragheb, Tianyi Yu, David Ma, Jason Helge Anderson:
Modeling and Exploration of Elastic CGRAs. 404-410 - Alexander Montgomerie-Corcoran, Zhewen Yu, Christos-Savvas Bouganis:
SAMO: Optimised Mapping of Convolutional Neural Networks to Streaming Architectures. 418-424 - Shashwat Khandelwal, Shanker Shreejith:
A Lightweight Multi-Attack CAN Intrusion Detection System on Hybrid FPGAs. 425-429 - Andrew Boutros, Eriko Nurvitadhi, Vaughn Betz:
RAD-Sim: Rapid Architecture Exploration for Novel Reconfigurable Acceleration Devices. 438-444 - Chen Wu, Zhuofu Tao, Kun Wang, Lei He:
SkeletonGCN: A Simple Yet Effective Accelerator For GCN Training. 445-451 - Lucas Bex, Furkan Turan, Michiel Van Beirendonck, Ingrid Verbauwhede:
Mining CryptoNight-Haven on the Varium C1100 Blockchain Accelerator Card. 452-453 - Frans Skarman, Oscar Gustafsson:
Spade: An HDL Inspired by Modern Software Languages. 454-455 - Ziying Ni, Ayesha Khalid, Máire O'Neill:
High Performance FPGA-based Post Quantum Cryptography Implementations. 456-457 - Najdet Charaf, Diana Göhringer:
A Framework for Intrinsic Evolvable Systems. 458-459 - Cornelia Wulf, Diana Göhringer:
Virtualization of Embedded Reconfigurable Systems. 460-461 - Donal Campbell, Ciara Rafferty, Ayesha Khalid, Máire O'Neill:
Acceleration of Post Quantum Digital Signature Scheme CRYSTALS-Dilithium on Reconfigurable Hardware. 462-463 - Bardia Babaei, Dirk Koch:
Precise Characterizing of FPGAs in Production Systems. 464-465 - Kaspar Mätas, Kristiyan Manev, Joseph Powell, Dirk Koch:
FPL Demo: Runtime Stream Processing with Resource-Elastic Pipelines on FPGAs. 466 - Morihiro Kuga, Masahiro Iida, Hideharu Amano:
FPL Demo: An FPGA-IP Prototype Chip for MEC devices. 467 - Myrtle Shah:
FPL Demo: Hot Reconfiguration - Partial Reconfiguration without Bounds. 468 - Joseph Powell, Kaspar Matas, Kristiyan Manev, Dirk Koch:
FPL Demo: FPGA Bitstream Virus Scanning. 469 - Marie Auffret, Erwei Wang, James J. Davis:
FPL Demo: Logic Shrinkage: A Neural Architecture Search-Based Approach to FPGA Netlist Generation. 470 - Zelin Wang, Ke Zhang, Yisong Chang, Yanlong Yin, Yuxiao Chen, Ran Zhao, Songyue Wang, Mingyu Chen, Yungang Bao:
FPL Demo: SERVE: Agile Hardware Development Platform with Cloud IDE and Cloud FPGAs. 471 - Akinobu Tomori, Yasunori Osana:
FPL Demo: Kyokko - An Aurora 64b66b compatible 100 Gbps Communication Controller. 472 - Takefumi Miyoshi, Keisuke Koike, Shinich Morisaka, Hidehisa Shiomi, Kazuhisa Ogawa, Yutaka Tabuchi, Makoto Negoro:
FPL Demo: A Flexible and Scalable Quantum-Classical Interface based on FPGAs. 473 - Jakub Cabal, Jiri Sikora, Stepán Friedl, Martin Spinler, Jan Korenek:
FPL Demo: 400G FPGA Packet Capture Based on Network Development Kit. 474
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