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2020 – today
- 2023
[j5]Yuanxing Yan, Yehua Ling, Kai Huang, Gang Chen:
An efficient real-time accelerator for high-accuracy DNN-based optical flow estimation in FPGA. J. Syst. Archit. 136: 102818 (2023)- [j4]Yu Zhang, Yi Zheng, Yehua Ling, Haitao Meng, Gang Chen:
A robust and real-time DNN-based multi-baseline stereo accelerator in FPGAs. J. Syst. Archit. 143: 102966 (2023) - [c5]Fangzhou Zhang, Mingyue Cui, Jiakang Zhang, Yehua Ling, Han Liu, Kai Huang:
Accelerated Optimization for Simulation of Brain Spiking Neural Network on GPGPUs. ICA3PP (6) 2023: 172-189 - [c4]Rihui Song, Silu Guo, Ni Liu, Yehua Ling, Jin Gong, Kai Huang:
Real-Time Instance Segmentation and Tip Detection for Neuroendoscopic Surgical Instruments. ICONIP (10) 2023: 579-593 - [c3]Rihui Song, Zhidong Tan, Hongli Liang, Yehua Ling, Gang Chen, Kai Huang, Jin Gong:
Dense Depth Estimation for Monocular Endoscope Robot with an Adaptive Baseline. SMC 2023: 4940-4946 - 2022
- [j3]Yehua Ling
, Tao He, Yu Zhang, Haitao Meng, Kai Huang, Gang Chen:
Lite-Stereo: A Resource-Efficient Hardware Accelerator for Real-Time High-Quality Stereo Estimation Using Binary Neural Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5357-5366 (2022) - [c2]Yehua Ling, Yuanxing Yan, Kai Huang, Gang Chen:
FlowAcc: Real-Time High-Accuracy DNN-based Optical Flow Accelerator in FPGA. DATE 2022: 112-115 - [c1]Yehua Ling, Yuanxing Yan, Kai Huang, Gang Chen:
Ultra-Flow: An Ultra-fast and High-quality Optical Flow Accelerator with Deep Feature Matching on FPGA. FPL 2022: 33-39 - 2021
- [j2]Yehua Ling, Tao He, Haitao Meng, Yu Zhang, Gang Chen:
Hardware accelerator for an accurate local stereo matching algorithm using binary neural network. J. Syst. Archit. 117: 102110 (2021) - 2020
- [j1]Gang Chen, Yehua Ling, Tao He, Haitao Meng, Shengyu He, Yu Zhang, Kai Huang:
StereoEngine: An FPGA-Based Accelerator for Real-Time High-Quality Stereo Estimation With Binary Neural Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 4179-4190 (2020)
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