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ORCIDICCD 2000: Austin, Texas, USA
- Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000. IEEE Computer Society 2000, ISBN 0-7695-0801-4
Keynote Address
- Dirk Friebel:
On the Road to a Mobile Information Society. 3-
Session 1.1: New Architectures
- Krishna Kant, Ravishankar K. Iyer, Prasant Mohapatra:
Architectural Impact of Secure Socket Layer on Internet Servers. 7-14 - Xiao Yang, Ruby B. Lee:
Fast Subword Permutation Instructions Using Omega and Flip Network Stages. 15-21 - Tor E. Jeremiassen:
Sleipnir - An Instruction-Level Simulator Generator. 23-31
Session 1.2: Fault-Simulation and ATPG at Different Design Levels
- Junwei Hou, Abhijit Chatterjee:
Analog Transient Concurrent Fault Simulation with Dynamic Fault Grouping. 35-41 - Dimitrios Kagaris, Spyros Tragoudas:
Pseudoexhaustive TPG with a Provably Low Number of LFSR Seeds. 42-47 - Fabrizio Ferrandi
, Donatella Sciuto, Alessandro Fin, Franco Fummi:
An Application of Genetic Algorithms and BDDs to Functional Testing. 48-56
Session 1.3: Advanced Design Techniques
- Chulwoo Kim, Jaesik Lee, Kwang-Hyun Baek, Eric Martina, Sung-Mo Kang:
High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) Technology. 59-64 - Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh:
Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-Micron CMOS Circuits. 65-72 - Simon W. Moore, George S. Taylor, Paul A. Cunningham, Robert D. Mullins, Peter Robinson:
Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems. 73-78
Session 2.1: Improving CPU Performance
- Martin Burtscher, Benjamin G. Zorn:
Hybridizing and Coalescing Load Value Predictors. 81-92 - Yul Chu, Mabo Robert Ito:
A 2-Way Thrashing-Avoidance Cache (TAC): An Efficient Instruction Cache Scheme for Object-Oriented Languages. 93-98 - J. Morris Chang, Witawas Srisa-an, Chia-Tien Dan Lo:
Architectural Support for Dynamic Memory Management. 99-104 - Masaaki Kondo, Hideki Okawara, Hiroshi Nakamura, Taisuke Boku:
SCIMA: Software Controlled Integrated Memory Architecture for High Performance Computing. 105-111
Session 2.2: Parasitic Modeling, Analysis, and Optimization
- Tong Xiao, Malgorzata Marek-Sadowska:
Worst Delay Estimation in Crosstalk Aware Static Timing Analysis. 115-120 - Payam Heydari, Massoud Pedram:
Analysis and Optimization of Ground Bounce in Digital CMOS Circuits. 121-126 - Nasser Masoumi, Safieddin Safavi-Naeini, Mohamed I. Elmasry:
An Efficient and Accurate Model for RF/Microwave Spiral Inductors Using Microstrip Lines Theory. 127-132 - Yanhong Yuan, Prithviraj Banerjee:
Comparative Study of Parallel Algorithms for 3-D Capacitance Extraction on Distributed Memory Multiprocessors. 133-138
Session 2.3: Low Power and Arithmetic
- Rolf Hakenes, Yiannos Manoli:
A Novel Low-Power Microprocessor Architecture. 141-146 - Rafael A. Moreno, Luis Piñuel, Silvia Del Pino, Francisco Tirado:
A Power Perspective of Value Speculation for Superscalar Microprocessors. 147-154 - Javier D. Bruguera, Tomás Lang:
Multilevel Reverse-Carry Adder. 155-162 - Deependra Talla, Lizy Kurian John, Viktor S. Lapinskii, Brian L. Evans:
Evaluating Signal Processing and Multimedia Applications on SIMD, VLIW and Superscalar Architectures. 163-172
Session 3.1: Servers and Parallelism
- Qiang Cao, Josep Torrellas, H. V. Jagadish:
Unified Fine-Granularity Buffering of Index and Data: Approach and Implementation. 175-186 - Jeffrey B. Rothman, Alan Jay Smith:
Analysis of Shared Memory Misses and Reference Patterns. 187-198 - John S. Seng, Dean M. Tullsen, George Z. N. Cai:
Power-Sensitive Multithreaded Architecture. 199-206
Session 3.2: Circuit Optimization and Analysis
- I-Min Liu, Adnan Aziz:
Delay Constrained Optimization by Simultaneous Fanout Tree Construction, Buffer Insertion/Sizing and Gate Sizing. 209-214 - Yi-Kan Cheng, David Bearden, Kanti Suryadevara:
Application-Based, Transistor-Level Full-Chip Power Analysis for 700 MHz PowerPCTM Microprocessor. 215-220 - José Luis Neves, Stephen T. Quay:
Buffer Library Selection. 221-226 - Naran Sirisantana, Liqiong Wei, Kaushik Roy:
High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness. 227-232
Session 3.3: Logic Circuit Families
- Sudhakar Bobba, Ibrahim N. Hajj:
Current-Mode Threshold Logic Gates. 235-240 - Alexandre Solomatnikov, Kaushik Roy, Cheng-Kok Koh, Dinesh Somasekhar:
Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family. 241-246 - Larry McMurchie, Su Kio, Gin Yee, Tyler Thorp, Carl Sechen:
Output Prediction Logic: A High-Performance CMOS Design Technique. 247-254
Keynote Address
- Gregory F. Pfister:
The Future of Populist Parallelism. 257
Session 4.1: Intelligent Memory
- Lars Friebe, Yoshikazu Yabe, Masato Motomura:
A Study of Channeled DRAM Memory Architectures. 261-266 - Haifeng Yu, Gershon Kedem:
DRAM-Page Based Prediction and Prefetching. 267-275 - Mark Oskin, Diana Keen, Justin Hensley, Lucian Vlad Lita, Frederic T. Chong:
Reducing Cost and Tolerating Defects in Page-based Intelligent Memory. 276-284
Session 4.2: Processor Microarchitecture
- Jung-Hoon Lee, Jang-Soo Lee, Shin-Dug Kim:
A Selective Temporal and Aggressive Spatial Cache System Based on Time Interval. 287-293 - Jih-Ching Chiu, I-Huan Huang, Chung-Ping Chung:
Design of Instruction Stream Buffer with Trace Support for X86 Processors. 294-299 - Anshuman S. Nadkarni, Akhilesh Tyagi:
A Trace Based Evaluation of Speculative Branch Decoupling. 300-307
Session 4.3: Digital Logic Techniques
- Hak-soo Yu, Songjun Lee, Jacob A. Abraham:
An Adder Using Charge Sharing and its Application in DRAMs. 311-317 - Shyh-Jye Jou, Hui-Hsuan Wang:
Fixed-Width Multiplier for DSP Application. 318-322 - Nikola Nedovic, Vojin G. Oklobdzija:
Dynamic Flip-Flop with Improved Power. 323-326
Session 5.1: Embedded Processors: Architecture and System-Design Issues
- Farinaz Koushanfar, Miodrag Potkonjak, Vandana Prabhu, Jan M. Rabaey:
Processors for Mobile Applications. 603-608 - Stephen B. Furber, David A. Edwards, Jim D. Garside:
AMULET3: A 100 MIPS Asynchronous Embedded Processor. 329-334 - Gülbin Ezer:
Xtensa with User Defined DSP Coprocessor Microarchitectures. 335-342 - Pavan Kumar, Mani B. Srivastava:
Predictive Strategies for Low-Power RTOS Scheduling. 343-348
Session 5.2: Floorplanning and Partitioning
- Guang-Ming Wu, Yun-Chih Chang, Yao-Wen Chang:
Rectilinear Block Placement Using B*-Trees. 351-356 - Abhishek Ranjan, Kia Bazargan, Majid Sarrafzadeh:
Fast Hierarchical Floorplanning with Congestion and Timing Control. 357-362 - Elie Yarack, Joan Carletta:
An Evaluation of Move-Based Multi-Way Partitioning Algorithms. 363-369 - Koji Ohashi, Mineo Kaneko, Satoshi Tayu:
Assignment-Space Exploration Approach to Concurrent Data-Path/Floorplan Synthesis. 370-375
Session 5.3: Basic Algorithms in Verification and Test
- Joonyoung Kim, Jesse Whittemore, Karem A. Sakallah:
On Solving Stack-Based Incremental Satisfiability Problems. 379-382 - Wolfgang Günther, Rolf Drechsler, Stefan Höreth:
Efficient Dynamic Minimization of Word-Level DDs Based on Lower Bound Computation. 383-388 - Irith Pomeranz, Sudhakar M. Reddy:
Sensitivity Levels of Test Patterns and Their Usefulness in Simulation-Based Test Generation. 389-394 - Irith Pomeranz, Sudhakar M. Reddy:
On Test Application Time and Defect Detection Capabilities of Test Sets for Scan Designs. 395-400
Session 6.1: Special Session: Advancements in DSP Architecture
- Tim Anderson, Sanjive Agarwala:
Effective Hardware-Based Two-Way Loop Cache for High Performance Low Power Processors. 403-407 - Sanjive Agarwala, Charles Fuoco, Tim Anderson, Dave Comisky, Christopher Mobley:
A Multi-Level Memory System Architecture for High-Performance DSP Applications. 408-413 - Dave Comisky, Sanjive Agarwala, Charles Fuoco:
A Scalable High-Performance DMA Architecture for DSP Applications. 414-419
Session 6.2: Advanced Architectural Design and Synthesis
- Srihari Cadambi, Seth Copen Goldstein:
Efficient Place and Route for Pipeline Reconfigurable Architectures. 423-429 - Makiko Itoh, Shigeaki Higaki, Yoshinori Takeuchi, Akira Kitajima, Masaharu Imai, Jun Sato, Akichika Shiomi:
PEAS-III: An ASIP Design Environment. 430-436 - Satish Pillai, Margarida F. Jacome:
Symbolic Binding for Clustered VLIW ASIPs. 437-444 - Dinesh Ramanathan, Rajesh K. Gupta, Raymond Roth:
Interfacing Hardware and Software Using C++ Class Libraries. 445-450
Session 6.3: Application and Case Studies in Test and Verification
- Hoon Choi, Myung-Kyoon Yim, Jae Young Lee, Byeong-Whee Yun, Yun-Tae Lee:
Formal Verification of an Industrial System-on-a-Chip. 453-458 - Viresh Paruthi, Andreas Kuehlmann:
Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation. 459-464 - Dirk W. Hoffmann, Thomas Kropf:
Efficient Design Error Correction of Digital Circuits. 465-472 - Michael Cogswell, Don Pearl, James Sage, Alan Troidl:
An Automatic Validation Methodology for Logic BIST in High Performance VLSI Design. 473-478
Invited Paper
- Hilary J. Kahn, R. B. E. Napper:
The Birth of the Baby. 481-486
Session 7.1: Logic Optimization
- Thomas Kutzschebauch:
Efficient Logic Optimization Using Regularity Extraction. 487-493 - Subarnarekha Sinha, Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks. 494-503 - Per Lindgren, Rolf Drechsler, Bernd Becker:
Minimization of Ordered Pseudo Kronecker Decision Diagrams. 504-510
Session 7.2: High Level Specification and Synthesis
- Wander O. Cesário, Ahmed Amine Jerraya, Zoltan Sugar, Imed Moussa:
Rethinking Behavioral Synthesis for a Better Integration within Existing Design Flows. 513-518 - Bong-Il Park, Hoon Choi, In-Cheol Park, Chong-Min Kyung:
Synthesis and Optimization of Interface Hardware between IP's Operating at Different Clock Frequencies. 519-524 - Fabiano Hessel, Philippe Coste, Gabriela Nicolescu, P. LeMarrec, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya:
Multi-Level Communication Synthesis of Heterogeneous Multilanguage Specification. 525-530
Poster Sessions
- Wael M. Badawy, Magdy A. Bayoumi:
Low Power Video Object Motion-Tracking Architecture for Very Low Bit Rate Online Video Applications. 533-536 - Alfredo Benso, Stefano Martinetto, Paolo Prinetto, Riccardo Mariani:
An SEU Injection Tool to Evaluate DSP-Based Architectures for Space Applications. 537-538 - Alfredo Benso, Stefano Di Carlo, Silvia Chiusano, Paolo Prinetto, Fabio Ricciato, Monica Lobetti Bodoni, Maurizio Spadari:
On Integrating a Proprietary and a Commercial Architecture for Optimal BIST Performances in SoCs. 539-540 - Haizhou Chen, Bing Lu, Ding-Zhu Du:
Static Timing Analysis with False Paths. 541-544 - Joachim Gerlach, Wolfgang Rosenstiel:
A Methodology and Tool for Automated Transformational High-Level Design Space Exploration. 545-548 - J. P. Grossman:
Cheap Out-of-Order Execution Using Delayed Issue. 549-551 - Steve Haynal, Forrest Brewer:
Representing and Scheduling Looping Behavior Symbolically. 552-555 - Toru Hiyama, Yuko Ito, Satoru Isomura, Kazunobu Nojiri, Eijiro Maeda:
Advanced Wiring RC Timing Design Techniques for Logic LSIs in Gigahertz Era and Beyond. 556-558 - Yoochang Jung, Stefan G. Berg, Donglok Kim, Yongmin Kim:
A Register File with Transposed Access Mode. 559-560 - Kamal S. Khouri, Niraj K. Jha:
Leakage Power Analysis and Reduction during Behavioral Synthesis. 561-564 - Austin Kim, J. Morris Chang:
An Advanced Instruction Folding Mechanism for a Stackless Java Processor. 565-566 - Hemang Lavana, Franc Brglez, Robert B. Reese, Gangadhar Konduri, Anantha P. Chandrakasan:
OpenDesign: An Open User-Configurable Project Environment for Collaborative Design and Execution on the Internet. 567-570 - Haris Lekatsas, Jörg Henkel, Wayne H. Wolf:
A Decompression Architecture for Low Power Embedded Systems. 571-574 - Rafael Maestre, Milagros Fernández, Román Hermida, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh:
Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures. 575-576 - Afzal Malik, Bill Moyer, Dan Cermak:
The M·CORETM M340 Unified Cache Architecture. 577-580 - Song-Ra Pan, Yao-Wen Chang:
Crosstalk-Constrained Performance Optimization by Using Wire Sizing and Perturbation. 581-584 - Marius Pirvu, Laxmi N. Bhuyan, Rabi N. Mahapatra:
Hierarchical Simulation of a Multiprocessor Architecture. 585-588 - Hagen Ploog, Dirk Timmermann:
On Multiple Precision Based Montgomery Multiplication without Precomputation of N0´ = -N0-1 mod W. 589-590 - Srivaths Ravi, Niraj K. Jha, Indradeep Ghosh, Vamsi Boppana:
A Technique for Identifying RTL and Gate-Level Correspondences. 591-594 - John T. Welch, Joan Carletta:
A Direct Mapping FPGA Architecture for Industrial Process Control Applications. 595-598 - Brian D. Winters, Alan J. Hu:
Source-Level Transformations for Improved Formal Verification. 599-602
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