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ORCIDVLSI Design, Volume 1
Volume 1, Number 1, 1993
- Editorial. i-ii
- Sunil R. Das:
Guest Editorial. iii-iv - About the Editor in Chief and the Guest Editor. v
- Earl E. Swartzlander Jr., Miroslaw Malek:
Overlapped Subarray Segmentation: An Efficient Test Method for Cellular Arrays. 1-7 - Rajiv Sharma, Kewal K. Saluja:
Theory, Analysis and Implementation of an On-Line BIST Technique. 9-22 - Jacob Savir, Paul H. Bardell:
Built-In Self-Test: Milestones and Challenges. 23-44 - Michael J. Bryan, Srinivas Devadas, Kurt Keutzer:
Analysis and Design of Regular Structures for Robust Dynamic Fault Testability. 45-60 - Walid A. Najjar
, Pradip K. Srimani:
Conditional Disconnection Probability in Star Graphs. 61-70 - Warren H. Debany Jr.:
Coverage of Node Shorts Using Internal Access and Equivalence Classes. 71-85 - Samiha Mourad:
Computer-Aided Testing Systems: Evaluation and Benchmark Circuits. 87-97
Volume 1, Number 2, 1994
- Marwan A. Jabri:
Building Rectangular Floorplans-A Graph Theoretical Approach. 99-111 - Sajjan G. Shiva, Judit U. Jones:
A VHDL Based Expert System for Hardware Synthesis. 113-126 - S. K. Nandy, R. B. Panwar:
Geometric Design Rule Check of VLSI Layouts in Mesh Connected Processors. 127-154 - S. K. Nandy:
Geometric Design Rule Check of VLSI Layouts in Distributed Computing Environment. 155-167 - Krishnamurthy Subramanian, Mehdi R. Zargham:
Distributed and Parallel Demand Driven Logic Simulation Algorithms. 169-179
Volume 1, Number 3, 1994
- Chien-In Henry Chen, Gerald E. Sobelman:
Cluster Partitioning Techniques for Data Path Synthesis. 181-192 - San-Yuan Wu, Sartaj Sahni:
Fast Algorithms to Partition Simple Rectilinear Polygons. 193-215 - Chien-In Henry Chen:
Using PDM on Multiport Memory Allocation in Data Path. 217-232 - Xiaoyu Song:
An Optimum Channel Routing Algorithm in the Knock-knee Diagonal Model. 233-242 - Inderpreet Bhasin, Joseph G. Tront:
Block-Level Logic Extraction from CMOS VLSI Layouts. 243-259
Volume 1, Number 4, 1994
- Rochit Rajsuman:
Special Issue on Digital Hardware Testing. i - Michael Ogbonna Esonu, Dhamin Al-Khalili, Côme Rozon:
Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS & BiCMOS Circuits. 261-276 - Yashwant K. Malaiya, Anura P. Jayasumana, Carol Q. Tong, Sankaran M. Menon:
Resolution Enhancement in IDDQ Testing for Large ICs. 277-284 - Michael J. Batek, John P. Hayes:
Optimal Testing and Design of Adders. 285-298 - Ben Mathew, Daniel G. Saab:
Partial Reset: An Alternative DFT Approach. 299-311 - Warren H. Debany Jr., Mark Gorniak, Anthony R. Macera, Daniel Daskiewich, Kevin A. Kwiat, Heather B. Dussault:
Empirical Bounds on Fault Coverage Loss Due to LFSR Aliasing. 313-326 - Rochit Rajsuman, Kamal Rajkanan:
STD Architecture: A Practical Approach to Test M-Bits Random Access Memories. 327-334 - Fadi Busaba, Parag K. Lala:
An Approach for Self-Checking Realization of Interacting Finite State Machines. 335-343 - Kevin T. Kornegay, Robert W. Brodersen:
Integrated Test Solutions for a System Design Environment. 345-357
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