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ORCIDThe Journal of VLSI Signal Processing, Volume 1
Volume 1, Number 1, August 1989
- Earl E. Swartzlander Jr.:
Editorial. 5 - Simon C. Knowles, John G. McWhirter, Roger F. Woods
, John V. McCanny:
Bit-Level systolic architectures for high performance IIR filtering. 9-24 - Takao Nishitani, Ichiro Tamitani, Hidenobu Harasaki, Yukio Endo, Toshiyuki Kanou, Koichi Kikuchi:
Parallel video signal processor configuration based on overlap-save technique and its LSI processor element: VISP. 25-34 - Nader Gharachorloo, Satish Gupta, Erdem Hokenek, Peruvemba Balasubramanian, William Bogholtz, Christian Mathieu, Christos Zoulas:
A million transistor systolic array graphics engine. 35-43 - K. Wojtek Przytula, J. Greg Nash:
Parallel implementation of synthetic aperture radar algorithms. 45-56 - Mitsuo Ishii, Hiroyuki Sato, Morio Ikesaka, Kouichi Murakami, Hiroaki Ishihata:
Cellular array processor CAP and applications. 57-67 - R. M. Lea:
ASP modules: cost-effective building-blocks for real-time DSP systems. 69-84
Volume 1, Number 2, October 1989
- Earl E. Swartzlander Jr.:
Editorial. 91 - José A. B. Fortes, Sun-Yuan Kung:
Introduction. 93-94 - Patrice Quinton, Vincent Van Dongen:
The mapping of linear recurrence equations on regular arrays. 95-113 - Yoav Yaacoby, Peter R. Cappello:
Scheduling a system of nonsingular affine recurrence equations onto a processor array. 115-125 - Vwani P. Roychowdhury, Thomas Kailath:
Subspace scheduling and parallel implementation of non-systolic regular iterative algorithms. 127-142 - Paul F. C. Krekel, Ed F. Deprettere:
A systolic algorithm and architecture for solving sets of linear equations with multi-band coefficient matrix. 143-152 - Fernando J. Nuñez, Mateo Valero:
A block algorithm and optimal fixed-size systolic array processor for the algebraic path problem. 153-162
Volume 1, Number 3, September 1989
- Earl E. Swartzlander Jr.:
Editorial. 167 - Franklin T. Luk, Eric K. Torng, Cynthia J. Anfinson:
A novel fault tolerance technique for recursive least squares minimization. 181-188 - Graham A. Jullien, P. D. Bird, J. T. Carr, Majid Taheri, William C. Miller:
An efficient bit-level systolic cell design for finite ring digital signal processing applications. 189-207 - Weijia Shang, José A. B. Fortes:
On the optimality of linear schedules. 209-220 - Jenq-Neng Hwang, Sun-Yuan Kung:
Parallel algorithms/architectures for neural networks. 6
Volume 1, Number 4, April 1990
- Giuseppe Alia, Enrico Martinelli:
A VLSI structure forX(modm) operation. 257-264 - Jef L. van Meerbergen, Jos Huisken, Paul E. R. Lippens, O. McArdle, R. Segers, Gert Goossens, Jan Vanhoof, Dirk Lanneer, Francky Catthoor, Hugo De Man:
An integrated automatic design system for complex DSP algorithms. 265-278 - Robert Schreiber:
Bidiagonalization and symmetric tridiagonalization by systolic arrays. 279-285 - Francky Catthoor, Dirk Lanneer, Hugo De Man:
Efficient microcoded processor design for fixed rate DFT and FFT. 287-306 - Oscar H. Ibarra, Tao Jiang, Jik H. Chang, Michael A. Palis:
Systolic algorithms for some scheduling and graph problems. 307-320 - Mary Jane Irwin, Robert Michael Owens:
A case for digit serial VLSI signal processors. 321-334 - V. K. Prasanna Kumar, Yu-Chen Tsai:
Mapping dynamic programming onto a linear systolic array. 335-343 - Teresa H.-Y. Meng, Robert W. Brodersen, David G. Messerschmitt:
A clock-free chip set for high-sampling rate adaptive filters. 345-365 - David E. van den Bout, Paul D. Franzon, John J. Paulos, Thomas K. Miller III, Wesley E. Snyder, H. Troy Nagle, Wentai Liu:
Scalable VLSI implementations for neural networks. 367-385
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