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ORCIDHandbook of Algorithms for Physical Design Automation 2008
- Charles J. Alpert, Dinesh P. Mehta
, Sachin S. Sapatnekar:
Handbook of Algorithms for Physical Design Automation. Auerbach Publications 2008, ISBN 978-0-8493-7242-1 - Charles J. Alpert, Dinesh P. Mehta, Sachin S. Sapatnekar:
Introduction to Physical Design. - Ralph H. J. M. Otten:
Layout Synthesis. - Frank Liu, Sachin S. Sapatnekar:
Metrics Used in Physical Design. - Dinesh P. Mehta, Hai Zhou:
Basic Data Structures. - Vishal Khandelwal, Ankur Srivastava:
Basic Algorithmic Techniques. - Zhi-Quan Luo:
Optimization Techniques for Circuit Design Applications. - Dorothy Kucar:
Partitioning and Clustering. - Susmita Sur-Kolay:
Floorplanning. - Ting-Chi Wang, Martin D. F. Wong:
Slicing Floorplans. - Evangeline F. Y. Young:
Floorplan Representations. - Tung-Chieh Chen, Yao-Wen Chang:
Packing Floorplan Representations. - Dinesh P. Mehta, Yan Feng:
Recent Advancesin Floorplanning. - Louis K. Scheffer:
Industrial Floorplanning and Prototyping. - Gi-Joon Nam, Paul G. Villarrubia:
Placement. - Jarrod A. Roy, Igor L. Markov:
Partitioning-Based Methods. - William Swartz:
Placement Using Simulated Annealing. - Ulrich Brenner, Jens Vygen:
Analytical Methods in Placement. - Andrew A. Kennings, Kristofer Vorwerk:
Force-Directed and Other Continuous Placement Methods. - Jason Cong, Joseph R. Shinnerl:
Enhancing Placement with Multilevel Techniques. - Ameya R. Agnihotri, Patrick H. Madden:
Legalization and Detailed Placement. - David Z. Pan, Bill Halpin, Haoxing Ren:
Timing-Driven Placement. - Saurabh N. Adya, Xiaojian Yang:
Congestion-Driven Physical Design. - Muhammet Mustafa Ozdal, Martin D. F. Wong:
Global Routing Formulation and Maze Routing. - Gabriel Robins, Alexander Zelikovsky:
Minimum Steiner Tree Construction. - Jiang Hu, Gabriel Robins, Cliff C. N. Sze:
Timing-Driven Interconnect Synthesis. - Jiang Hu, Zhuo Li, Shiyan Hu:
Buffer Insertion Basics. - Milos Hrkic, John Lillis:
Generalized Buffer Insertion. - Jiang Hu, Cliff C. N. Sze:
Buffering in the Layout Environment. - Sanghamitra Roy, Charlie Chung-Ping Chen:
Wire Sizing. - Rupesh S. Shelar, Prashant Saxena:
Estimation of Routing Congestion. - Jeffrey S. Salowe:
Rip-Up and Reroute. - Christoph Albrecht:
Optimization Techniquesin Routing. - Cheng-Kok Koh, Evangeline F. Y. Young, Yao-Wen Chang:
Global Interconnect Planning. - Rajendran Panda, Vladimir Zolotov, Murat R. Becer:
Coupling Noise. - Franklin M. Schellenberg:
Modeling and Computational Lithography. - Andrew B. Kahng, Kambiz Samadi:
CMP Fill Synthesis. - Puneet Gupta, Evanthia Papadopoulou:
Yield Analysis and Optimization. - Minsik Cho, Joydeep Mitra, David Z. Pan:
Manufacturability-Aware Routing. - Charles J. Alpert, Nathaniel Hieter, Arjen Mets, Ruchir Puri, Lakshmi N. Reddy, Haoxing Ren, Louise Trevillyan:
Placement-Driven Synthesis Design Closure Tool. - Steve Teig, Asmus Hetzel, Joseph L. Ganley, Jon Frankle, Aki Fujimura:
X Architecture Place and Route. - Yehea I. Ismail:
Inductance Effects in Global Nets. - Chris C. N. Chu, Min Pan:
Clock Network Design. - Chris C. N. Chu, Min Pan:
Practical Issues in Clock Network Design. - Haihua Su, Sani R. Nassif:
Power Grid Design. - Steven J. E. Wilton, Nathalie Chan King Choy, Scott Y. L. Chin, Kara K. W. Poon:
Field-Programmable Gate Array Architectures. - Kia Bazargan:
FPGA Technology Mapping, Placement, and Routing. - Kia Bazargan, Sachin S. Sapatnekar:
Physical Design for Three-Dimensional Circuits.
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