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ORCIDCharlie Chung-Ping Chen
Chung-Ping Chen
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- affiliation: University of Wisconsin, USA
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2020 – today
- 2023
[j23]Sheng-Jen Cheng
, Pi-Neng Shen, Chung-Hung Hong, Zheng-Wei Chen, Chung-Ping Chen, Sheng-Lyang Jang:
Injection-Locked Frequency Sixtuplers in 90 nm CMOS by Using the Push-Push Doubler. IEEE Access 11: 130048-130059 (2023)- [c92]Sheng-Jen Cheng, Chieh-Ju Tsai, Sheng-Yu Wang, Wei-Yi Liu, Chung-Ping Chen:
A Ripple-Based Constant On-Time Controlled DC-DC Buck Converter with Inductor Current Sensing Technique. ISCAS 2023: 1-5 - 2022
- [c91]Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Charlie Chung-Ping Chen:
Intelligent Design Automation for Heterogeneous Integration. ISPD 2022: 105-106 - 2021
- [c90]Chun-Chang Yu, Yu Hen Hu, Yi-Chang Lu, Charlie Chung-Ping Chen:
Power Reduction of a Set-Associative Instruction Cache Using a Dynamic Early Tag Lookup. DATE 2021: 1799-1802 - [c89]Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Chung-Ping Chen:
Opportunities for 2.5/3D Heterogeneous SoC Integration. VLSI-DAT 2021: 1 - 2020
- [j22]Chung-Yi Ting, Jing-Yuan Lin, Charlie Chung-Ping Chen:
A Quasi-V2 Hysteretic Buck Converter With Adaptive COT Control for Fast DVS and Load-Transient Response in RF Applications. IEEE Trans. Circuits Syst. II Express Briefs 67-II(3): 531-535 (2020) - [c88]Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Chung-Ping Chen:
Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration. ICCAD 2020: 125:1-125:7
2010 – 2019
- 2019
- [j21]Shih-Lun Huang, Sheng-Yi Hung, Chung-Ping Chen:
Frequency Hopping and Parallel Driving With Random Delay Especially Suitable for the Charger Noise Problem in Mutual-Capacitive Touch Applications. IEEE Access 7: 3980-3993 (2019) - [j20]Yi-Chieh Hsu, Chung-Yi Ting, Li-Sheng Hsu, Jing-Yuan Lin, Charlie Chung-Ping Chen:
A Transient Enhancement DC-DC Buck Converter With Dual Operating Modes Control Technique. IEEE Trans. Circuits Syst. II Express Briefs 66-II(8): 1376-1380 (2019) - [c87]Jih-Yi Liao, Der-Chin Chen, Shih-Tsung Chang, Chung-Ping Chen, Chao-Han Wu, Cheng-Ke Hsu:
Subjective Interpupillary Distance of Measurement Technique. ISPACS 2019: 1-2 - 2018
- [c86]Shuo-Hong Hung, Ina Wu, Yi-Chen Li, Cheng-Ta Li, Charlie Chung-Ping Chen:
A Real Time EEG Analysis System for the Prediction of Clinical Antidepressant Responses. DSP 2018: 1-5 - 2017
- [c85]Shih-Lun Huang, Sheng-Yi Hung, Chung-Ping Chen:
An efficient DFT-based algoritiim for the charger noise problem in capacitive touch applications. ISCAS 2017: 1-4 - 2016
- [j19]Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen:
A 6.7 MHz to 1.24 GHz 0.0318 mm 2 Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS. IEEE J. Solid State Circuits 51(2): 412-427 (2016) - [c84]Pei-Chun Lin, Yu-Hsuan Pai, Yu-Hsiang Chiu, Shao-Yuan Fang, Charlie Chung-Ping Chen:
Lossless compression algorithm based on dictionary coding for multiple e-beam direct write system. DATE 2016: 285-288 - 2015
- [c83]Shih-Lun Huang, Sheng-Yi Hung, Chung-Ping Chen:
Clustering-based multi-touch algorithm framework for the tracking problem with a large number of points. DATE 2015: 719-724 - [c82]Chung-Ping Chen, Guan-Jhong Lin, Yen-Hsemg Lin, Huai-Ping Song:
Bandwidth performance analysis with a variation of Webpage sizes. ICMLC 2015: 494-498 - [c81]Shuo-Hong Hung, Wei-Hao Kao, Kuan-I Wu, Yi-Wei Huang, Min-Han Hsieh, Charlie Chung-Ping Chen:
A 160MHz-to-2GHz low jitter fast lock all-digital DLL with phase tracking technique. ISCAS 2015: 553-556 - [c80]Ai Chien, Shuo-Hong Hung, Kuan-I Wu, Chang-Yi Liu, Min-Han Hsieh, Charlie Chung-Ping Chen:
A 8.1/5.4/2.7/1.62 Gb/s receiver for DisplayPort Version 1.3 with automatic bit-rate tracking scheme. ISCAS 2015: 2393-2396 - [c79]Kuan-I Wu, Szu-Yao Hung, Shuo-Hong Hung, Charlie Chung-Ping Chen:
A fast-settling high linearity auto gain control for broadband OFDM-based PLC system. ISCAS 2015: 2852-2855 - [c78]Kuan-I Wu, I-Shing Shen, Christina F. Jou, Charlie Chung-Ping Chen:
A -194 dBc/Hz FOM interactive current-reused QVCO (ICR-QVCO) with capacitor-coupling self-switching sinusoidal current biasing (CSSCB) phase noise reduction technique. VLSIC 2015: 236- - 2014
- [c77]Chun-Chang Yu, Chia-Hao Cheng, Pei-Chun Lin, Charlie Chung-Ping Chen:
Cost-efficient hardware implementation of stereo image depth optimization system. IC3D 2014: 1-6 - [c76]Shih-Lun Huang, Sheng-Yi Hung, Charlie Chung-Ping Chen, Cheng-Han Tsao, Nai-Wen Chang:
An efficient multi-touch tracking algorithm with a large number of points. ICCE-Berlin 2014: 429-430 - [c75]Kuan-I Wu, Shuo-Hong Hung, Shang-Yu Shieh, Bor-Tsang Hwang, Szu-Yao Hung, Charlie Chung-Ping Chen:
Current-mode adaptively hysteretic control for buck converters with fast transient response and improved output regulation. ISCAS 2014: 950-953 - 2013
- [c74]Pang-Kai Liu, Szu-Yao Hung, Chang-Yi Liu, Min-Han Hsieh, Charlie Chung-Ping Chen:
A 52 dBc MTPR line driver for powerline communication HomePlug AV standard in 0.18-μm CMOS technology. ISCAS 2013: 1404-1407 - [c73]Wei-Sheng Cheng, Min-Han Hsieh, Shuo-Hong Hung, Szu-Yao Hung, Charlie Chung-Ping Chen:
A 10-bit current-steering DAC for HomePlug AV2 powerline communication system in 90nm CMOS. ISCAS 2013: 2034-2037 - [c72]Szu-Yao Hung, Kai-Hsiang Chan, Charlie Chung-Ping Chen:
A high dynamic range programmable gain amplifier for HomePlug AV powerline communication system. ISCAS 2013: 2715-2718 - 2012
- [j18]Dongkeun Oh, Charlie Chung-Ping Chen, Yu Hen Hu:
Efficient Thermal Simulation for 3-D IC With Thermal Through-Silicon Vias. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(11): 1767-1771 (2012) - [j17]Yu-Shun Wang, Min-Han Hsieh, James Chien-Mo Li, Charlie Chung-Ping Chen:
An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(8): 1644-1655 (2012) - [c71]Chung-Ping Chen, Ying-Wen Bai, Hsiang-Hsiu Peng:
Equivalent bandwidth model of parallel servers with a variation of CPU loads, system response time and number of users. CCECE 2012: 1-6 - [c70]Min-Han Hsieh, Bing-Feng Lin, Yu-Shun Wang, Hao-Huei Chang, Charlie Chung-Ping Chen:
A 2 - 8 GHz multi-phase distributed DLL using phase insertion in 90 nm. ISCAS 2012: 2015-2018 - [c69]Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen:
A 6.7MHz-to-1.24GHz 0.0318mm2 fast-locking all-digital DLL in 90nm CMOS. ISSCC 2012: 244-246 - 2011
- [c68]Chia-Ping Shen, Chih-Min Chan, Feng-Sheng Lin, Ming-Jang Chiu, Jeng-Wei Lin, Jui-Hung Kao, Chung-Ping Chen, Feipei Lai:
Epileptic Seizure Detection for Multichannel EEG Signals with Support Vector Machines. BIBE 2011: 39-43 - [c67]Yu-Shun Wang, Min-Han Hsieh, Chia-Ming Liu, Chi-Wei Liu, James Chien-Mo Li, Charlie Chung-Ping Chen:
An at-speed self-testable technique for the high speed domino adder. CICC 2011: 1-4 - [c66]Yu-Shun Wang, Min-Han Hsieh, Chia-Ming Liu, Yi-Chi Wu, Bing-Feng Lin, Hsien-Chen Chiu, Charlie Chung-Ping Chen:
A 1.2V 6.4GHz 181ps 64-bit CD domino adder with DLL measurement technique. ISCAS 2011: 1423-1426 - [c65]Yu-Shun Wang, Min-Han Hsieh, Yi-Chi Wu, Chia-Ming Liu, Hsien-Chen Chiu, Bing-Feng Lin, Charlie Chung-Ping Chen:
A 12 Gb/s chip-to-chip AC coupled transceiver. ISCAS 2011: 1692-1695 - 2010
- [j16]Jui-Hsiang Liu, Ming-Feng Tsai, Lumdo Chen, Charlie Chung-Ping Chen:
Accurate and Analytical Statistical Spatial Correlation Modeling Based on Singular Value Decomposition for VLSI DFM Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(4): 580-589 (2010) - [c64]Dongkeun Oh, Nam Sung Kim, Charlie Chung-Ping Chen, Azadeh Davoodi, Yu Hen Hu:
Runtime temperature-based power estimation for optimizing throughput of thermal-constrained multi-core processors. ASP-DAC 2010: 593-599 - [c63]Jun-Kuei Zeng, Chung-Ping Chen:
Interconnect delay and slew metrics using the beta distribution. DATE 2010: 1329-1332 - [c62]Jun-Kuei Zeng, Chung-Ping Chen:
Interconnect delay and slew metrics using the extreme value distribution. ISQED 2010: 818-823 - [c61]Dongkeun Oh, Charlie Chung-Ping Chen, Nam Sung Kim, Yu Hen Hu:
The compatibility analysis of thread migration and DVFS in multi-core processor. ISQED 2010: 866-871
2000 – 2009
- 2008
- [c60]Sanghamitra Roy, Yu Hen Hu, Charlie Chung-Ping Chen, Shih-Pin Hung, Tse-Yu Chiang, Jiuan-Guei Tseng:
An optimal algorithm for sizing sequential circuits for industrial library based designs. ASP-DAC 2008: 148-151 - [c59]Tuck Boon Chan, Hsinchia Lu, Jun-Kuei Zeng, Charlie Chung-Ping Chen:
LTCC spiral inductor modeling, synthesis, and optimization. ASP-DAC 2008: 768-771 - [c58]Jui-Hsiang Liu, Ming-Feng Tsai, Lumdo Chen, Charlie Chung-Ping Chen:
Accurate and analytical statistical spatial correlation modeling for VLSI DFM applications. DAC 2008: 694-697 - [c57]Jun-Kuei Zeng, Chung-Ping Chen:
Deep Submicron Interconnect Timing Model with Quadratic Random Variable Analysis. DATE 2008: 1091-1094 - [c56]Jui-Hsiang Liu, Jun-Kuei Zeng, Ai-Syuan Hong, Lumdo Chen, Charlie Chung-Ping Chen:
Process-Variation Statistical Modeling for VLSI Timing Analysis. ISQED 2008: 730-733 - [c55]Chung-Ping Chen, Ying-Wen Bai, Yin-Sheng Lee:
Performance measurement and queueing analysis of medium-high blocking probability of two and three parallel connection servers. LCN 2008: 568-569 - [r1]Sanghamitra Roy, Charlie Chung-Ping Chen:
Wire Sizing. Handbook of Algorithms for Physical Design Automation 2008 - 2007
- [j15]Sanghamitra Roy, Weijen Chen, Charlie Chung-Ping Chen, Yu Hen Hu:
Numerically Convex Forms and Their Application in Gate Sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9): 1637-1647 (2007) - [c54]Sanghamitra Roy, Charlie Chung-Ping Chen:
SmartSmooth: A linear time convexity preserving smoothing algorithm for numerically convex data with application to VLSI design. ASP-DAC 2007: 559-564 - [c53]Dongkeun Oh, Charlie Chung-Ping Chen, Yu Hen Hu:
3DFFT: Thermal Analysis of Non-Homogeneous IC Using 3D FFT Green Function Method. ISQED 2007: 567-572 - 2006
- [j14]Jeng-Liang Tsai, Charlie Chung-Ping Chen, Guoqiang Chen, Brent Goplen, Haifeng Qian, Yong Zhan, Sung-Mo Kang, Martin D. F. Wong, Sachin S. Sapatnekar:
Temperature-Aware Placement for SOCs. Proc. IEEE 94(8): 1502-1518 (2006) - [j13]Lizheng Zhang, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen:
Statistical static timing analysis with conditional linear MAX/MIN approximation and extended canonical timing model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 1183-1191 (2006) - [j12]Lizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubner, Charlie Chung-Ping Chen:
Correlation-Preserved Statistical Timing With a Quadratic Form of Gaussian Variables. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2437-2449 (2006) - [c52]Lizheng Zhang, Jeng-Liang Tsai, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen:
Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops. ASP-DAC 2006: 941-946 - [c51]Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen:
Statistical timing analysis with path reconvergence and spatial correlations. DATE 2006: 528-532 - [c50]Pei-Yu Huang, Yu-Min Lee, Jeng-Liang Tsai, Charlie Chung-Ping Chen:
Simultaneous area minimization and decaps insertion for power delivery network using adjoint sensitivity analysis with IEKS method. ISCAS 2006 - [c49]Lizheng Zhang, Jun Shao, Charlie Chung-Ping Chen:
Non-gaussian statistical parameter modeling for SSTA with confidence interval analysis. ISPD 2006: 33-38 - [c48]Sanghamitra Roy, Charlie Chung-Ping Chen:
ConvexSmooth: A simultaneous convex fitting and smoothing algorithm for convex optimization problems. ISQED 2006: 665-670 - 2005
- [j11]Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja:
Yield-Driven, False-Path-Aware Clock Skew Scheduling. IEEE Des. Test Comput. 22(3): 214-222 (2005) - [j10]Yu-Min Lee, Yahong Cao, Tsung-Hao Chen, Janet Meiling Wang, Charlie Chung-Ping Chen:
HiPRIME: hierarchical and passivity preserved interconnect macromodeling engine for RLKC power delivery. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(6): 797-806 (2005) - [j9]Rong Jiang, Wenyin Fu, Charlie Chung-Ping Chen:
EPEEC: comprehensive SPICE-compatible reluctance extraction for high-speed interconnects above lossy multilayer substrates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(10): 1562-1571 (2005) - [c47]Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen:
Wave-pipelined on-chip global interconnect. ASP-DAC 2005: 127-132 - [c46]Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen:
Block based statistical timing analysis with extended canonical timing model. ASP-DAC 2005: 250-253 - [c45]Hsinwei Chou, Yu-Hao Wang, Charlie Chung-Ping Chen:
Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation. ASP-DAC 2005: 381-386 - [c44]Rong Jiang, Charlie Chung-Ping Chen:
Comprehensive frequency dependent interconnect extraction and evaluation methodology. ASP-DAC 2005: 1070-1073 - [c43]Jeng-Liang Tsai, Charlie Chung-Ping Chen:
Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling. ASP-DAC 2005: 1168-1171 - [c42]Lizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubner, Charlie Chung-Ping Chen:
Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model. DAC 2005: 83-88 - [c41]Rong Jiang, Yi-Hao Chang, Charlie Chung-Ping Chen:
ICCAP: a linear time sparse transformation and reordering algorithm for 3D BEM capacitance extraction. DAC 2005: 163-166 - [c40]Lizheng Zhang, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen:
Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model. DATE 2005: 952-957 - [c39]Vikas Sharma, Chien-Liang Chen, Chung-Ping Chen:
1-V 7-mW dual-band fast-locked frequency synthesizer. ACM Great Lakes Symposium on VLSI 2005: 431-435 - [c38]Rong Jiang, Wenyin Fu, Janet Meiling Wang, Vince Lin, Charlie Chung-Ping Chen:
Efficient statistical capacitance variability modeling with orthogonal principle factor analysis. ICCAD 2005: 683-690 - [c37]Janet Meiling Wang, Bharat Srinivas, Dongsheng Ma, Charlie Chung-Ping Chen, Jun Li:
System-level power and thermal modeling and analysis by orthogonal polynomial based response surface approach (OPRS). ICCAD 2005: 728-735 - [c36]Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja:
False Path and Clock Scheduling Based Yield-Aware Gate Sizing. VLSI Design 2005: 423-426 - 2004
- [j8]Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen:
Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(4): 565-572 (2004) - [c35]Clement Luk, Tsung-Hao Chen, Charlie Chung-Ping Chen:
Frequency-dependent reluctance extraction. ASP-DAC 2004: 792-797 - [c34]Rong Jiang, Charlie Chung-Ping Chen:
EPEEC: a compact reluctance based interconnect model considering lossy substrate eddy currents. CICC 2004: 493-496 - [c33]Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen:
Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining. DAC 2004: 904-907 - [c32]Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen:
Thermal and Power Integrity Based Power/Ground Networks Optimization. DATE 2004: 830-835 - [c31]Rong Jiang, Charlie Chung-Ping Chen:
SCORE: SPICE COmpatible Reluctance Extraction. DATE 2004: 948-953 - [c30]Rong Jiang, Charlie Chung-Ping Chen:
Realizable Reduction for Electromagnetically Coupled RLMC Interconnects. DATE 2004: 1400-1401 - [c29]Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja:
A yield improvement methodology using pre- and post-silicon statistical clock scheduling. ICCAD 2004: 611-618 - [c28]Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen:
Sensitivity guided net weighting for placement driven synthesis. ISPD 2004: 124-131 - [c27]Ting-Yuan Wang, Charlie Chung-Ping Chen:
SPICE-Compatible Thermal Simulation with Lumped Circuit Modeling for Thermal Reliability Analysis Based on Modeling Order Reduction. ISQED 2004: 357-362 - 2003
- [j7]Tsung-Hao Chen, Clement Luk, Charlie Chung-Ping Chen:
INDUCTWISE: inductance-wise interconnect simulator and extractor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(7): 884-894 (2003) - [j6]Yu-Min Lee, Charlie Chung-Ping Chen:
The power grid transient simulation in linear time based on 3-D alternating-direction-implicit method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(11): 1545-1550 (2003) - [j5]Ting-Yuan Wang, Charlie Chung-Ping Chen:
Thermal-ADI - a linear-time chip-level dynamic thermal-simulation algorithm based on alternating-direction-implicit (ADI) method. IEEE Trans. Very Large Scale Integr. Syst. 11(4): 691-700 (2003) - [c26]Yu-Min Lee, Charlie Chung-Ping Chen:
A hierarchical analysis methodology for chip-level power delivery with realizable model reduction. ASP-DAC 2003: 614-618 - [c25]Yu-Min Lee, Charlie Chung-Ping Chen:
The Power Grid Transient Simulation in Linear Time Based on 3D Alternating-Direction-Implicit Method . DATE 2003: 11020-11025 - [c24]Tsung-Hao Chen, Clement Luk, Charlie Chung-Ping Chen:
SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation. ICCAD 2003: 786-792 - [c23]Rong Jiang, Tsung-Hao Chen, Charlie Chung-Ping Chen:
PODEA: Power delivery efficient analysis with realizable model reduction. ISCAS (4) 2003: 608-611 - [c22]Ting-Yuan Wang, Yu-Min Lee, Charlie Chung-Ping Chen:
3D thermal-ADI: an efficient chip-level transient thermal simulator. ISPD 2003: 10-17 - [c21]Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen:
Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time. ISPD 2003: 166-173 - 2002
- [j4]Yu-Min Lee, Charlie Chung-Ping Chen:
Power grid transient simulation in linear time based on transmission-line-modeling alternating-direction-implicit method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(11): 1343-1352 (2002) - [j3]Ting-Yuan Wang, Charlie Chung-Ping Chen:
3-D Thermal-ADI: a linear-time chip level transient thermal simulator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(12): 1434-1445 (2002) - [j2]Yu-Min Lee, Charlie Chung-Ping Chen, Yao-Wen Chang, Martin D. F. Wong:
Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation. VLSI Design 15(3): 587-594 (2002) - [c20]Yahong Cao, Yu-Min Lee, Tsung-Hao Chen, Charlie Chung-Ping Chen:
HiPRIME: hierarchical and passivity reserved interconnect macromodeling engine for RLKC power delivery. DAC 2002: 379-384 - [c19]Tsung-Hao Chen, Clement Luk, Hyungsuk Kim, Charlie Chung-Ping Chen:
INDUCTWISE: inductance-wise interconnect simulator and extractor. ICCAD 2002: 215-220 - [c18]Ting-Yuan Wang, Charlie Chung-Ping Chen:
Optimization of the Power/Ground Network Wire-Sizing and Spacing Based on Sequential Network Simplex Algorithm. ISQED 2002: 157-162 - [c17]Charlie Chung-Ping Chen, Ed Cheng:
Future SoC Design Challenges and Solutions (invited). ISQED 2002: 534-538 - 2001
- [c16]Yu-Min Lee, Hing Yin Lai, Charlie Chung-Ping Chen:
Optimal spacing and capacitance padding for general clock structures. ASP-DAC 2001: 115-119 - [c15]Tsung-Hao Chen, Charlie Chung-Ping Chen:
Efficient Large-Scale Power Grid Analysis Based on Preconditioned Krylov-Subspace Iterative Methods. DAC 2001: 559-562 - [c14]Yu-Min Lee, Charlie Chung-Ping Chen:
Hierarchical model order reduction for signal-integrity interconnect synthesis. ACM Great Lakes Symposium on VLSI 2001: 109-114 - [c13]Yu-Min Lee, Charlie Chung-Ping Chen:
Power Grid Transient Simulation in Linear Time Based on Transmission-Line-Modeling Alternating-Direction-Implicit Method. ICCAD 2001: 75- - [c12]Saisanthosh Balakrishnan, Jong Hyuk Park, Hyungsuk Kim, Yu-Min Lee, Charlie Chung-Ping Chen:
Linear Time Hierarchical Capacitance Extraction without Multipole Expansion. ICCD 2001: 98-103 - [c11]Pradeepsunder Ganesh, Charlie Chung-Ping Chen:
RC-in RC-out Model Order Reduction Accurate up to Second Order Moments. ICCD 2001: 505-506 - [c10]Ting-Yuan Wang, Charlie Chung-Ping Chen:
Thermal-ADI: a linear-time chip-level dynamic thermal simulation algorithm based on alternating-direction-implicit (ADI) method. ISPD 2001: 238-243 - 2000
- [c9]Charlie Chung-Ping Chen, Tae-Woo Lee, Narayanan Murugesan, Susan C. Hagness:
Generalized FDTD-ADI: An Unconditionally Stable Full-Wave Maxwell's Equations Solver for VLSI Interconnect Modeling. ICCAD 2000: 156-163
1990 – 1999
- 1999
- [j1]Chung-Ping Chen, Chris C. N. Chu, Martin D. F. Wong:
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(7): 1014-1025 (1999) - [c8]Chung-Ping Chen, D. F. Wong:
Error Bounded Padé Approximation via Bilinear Conformal Transformation. DAC 1999: 7-12 - [c7]Chung-Ping Chen, Noel Menezes:
Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching. DAC 1999: 502-506 - [c6]Noel Menezes, Chung-Ping Chen:
Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect. VLSI Design 1999: 476- - 1998
- [c5]Chung-Ping Chen, Chris C. N. Chu, D. F. Wong:
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. ICCAD 1998: 617-624 - 1997
- [c4]Chung-Ping Chen, D. F. Wong:
Optimal Wire-Sizing Function with Fringing Capacitance Consideration. DAC 1997: 604-607 - 1996
- [c3]Chung-Ping Chen, Yao-Wen Chang, D. F. Wong:
Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation. DAC 1996: 405-408 - [c2]Chung-Ping Chen, Yao-Ping Chen, D. F. Wong:
Optimal Wire-Sizing Formular Under the Elmore Delay Model. DAC 1996: 487-490 - [c1]Chung-Ping Chen, Hai Zhou, D. F. Wong:
Optimal non-uniform wire-sizing under the Elmore delay model. ICCAD 1996: 38-43
Coauthor Index
Yu Hen Hu
aka: Yuhen Hu
aka: Yuhen Hu
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