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2020 – today
- 2021
[j32]Koppaka Ganesh Sai Apuroop, Anh Vu Le
, Mohan Rajesh Elara, Bing J. Sheu:
Reinforcement Learning-Based Complete Area Coverage Path Planning for a Modified hTrihex Robot. Sensors 21(4): 1067 (2021)- [j31]Vinu Sivanantham, Anh Vu Le, Yuyao Shi, Mohan Rajesh Elara, Bing J. Sheu:
Adaptive Floor Cleaning Strategy by Human Density Surveillance Mapping with a Reconfigurable Multi-Purpose Service Robot. Sensors 21(9): 2965 (2021)
2010 – 2019
- 2015
- [c35]P. Yue, Bing J. Sheu, A. Matsuzawa, K. Asada, L. Loh, Kofi A. A. Makinwa, Shekhar Borkar, Vladimir Stojanovic:
Circuits evening panel discussion 1: Is university circuit design research and education keeping up with industry needs? VLSIC 2015: 220-
2000 – 2009
- 2002
- [c34]Alex Yoondong Park, Steve H. Jen, Bing J. Sheu, Heesook Yoon, In Gyeom Kim:
An efficient parameter extraction method using statistical optimization in S-CMOS deep-submicron/nanometer model. ISCAS (5) 2002: 233-236 - 2001
- [j30]Theodore W. Berger, Michel Baudry, Roberta Diaz Brinton, Jim-Shih Liaw, Vasilis Z. Marmarelis, Alex Yoondong Park, Bing J. Sheu, Armand R. Tanguay:
Brain-implantable biomimetic electronics as the next era in neural prosthetics. Proc. IEEE 89(7): 993-1012 (2001) - [c33]Andrew B. Kahng, Bing J. Sheu, Nancy Nettleton, John M. Cohn, Shekhar Borkar, Louis Scheffer, Ed Cheng, Sang Wang:
Panel: Is Nanometer Design Under Control? DAC 2001: 591-592 - 2000
- [c32]Alex Yoondong Park, Jim-Shih Liaw, Theodore W. Berger, Bing J. Sheu:
Compact VLSI Neural Network Circuit with High-Capacity Dynamic Synapses. IJCNN (4) 2000: 214-218
1990 – 1999
- 1999
- [j29]Steve H. Jen, Bing J. Sheu, Yoondong Park:
A unified submicrometer MOS transistor charge/capacitance model for mixed-signal IC's. IEEE J. Solid State Circuits 34(1): 103-106 (1999) - 1998
- [j28]Steve H. Jen, Bing J. Sheu:
A compact and unified MOS DC current model with highly continuous conductances for low-voltage ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(2): 169-172 (1998) - 1997
- [j27]Bing J. Sheu, Mohammed Ghanbari, Horng-Dar Lin, Chung-Yu Wu:
Guest Editorial. IEEE Trans. Circuits Syst. Video Technol. 7(4): 571-574 (1997) - [j26]David Cheng-Hsiung Chen, Bing J. Sheu, Wayne C. Young:
A CDMA communication detector with robust near-far resistance using paralleled array processors. IEEE Trans. Circuits Syst. Video Technol. 7(4): 654-662 (1997) - [j25]Richard H. Tsai, Bing J. Sheu, Andrew Kostrzewski, Jeongdal Kim:
Advances in efficient optical links to enhance desktop multimedia processor systems. IEEE Trans. Circuits Syst. Video Technol. 7(4): 707-713 (1997) - [c31]Wai-Chi Fang, Guang Yang, Bedabrata Pain, Bing J. Sheu:
A Low Power Smart Vision System Based on Active Pixel Sensor Integrated with Programmable Neural Processor. ICCD 1997: 429-434 - 1996
- [j24]Sa Hyun Bang, Bing J. Sheu, Tony H. Wu:
Optimal solutions for cellular neural networks by paralleled hardware annealing. IEEE Trans. Neural Networks 7(2): 440-454 (1996) - [c30]David C. Chen, Bing J. Sheu, Theodore W. Berger:
A Compact Neural Network Based CDMA Receiver for Multimedia Wireless Communication. ICCD 1996: 99-103 - [c29]Richard H. Tsai, Bing J. Sheu, Theodore W. Berger:
VLSI design for real-time signal processing based on biologically realistic neural models. ICNN 1996: 676-681 - [c28]David C. Chen, Bing J. Sheu, Eric Y. Chou:
A neural network communication equalizer with optimized solution capability. ICNN 1996: 1957-1962 - 1995
- [c27]Eric Y. Chou, Bing J. Sheu, Tony H. Wu, Robert C. Chang:
VLSI design of densely-connected array processors. ICCD 1995: 492-497 - [c26]Wai-Chi Fang, Bing J. Sheu, Holger Venus, Rainer Sandau:
Smart-pixel array processors based on optimal cellular neural networks for space sensor applications. ICCD 1995: 703-708 - [c25]Richard H. Tsai, Eric Y. Chou, Bing J. Sheu, Theodore W. Berger:
A hippocampal model implementation using VLSI table-look-up and model-based approaches. ICNN 1995: 1508-1512 - [c24]Eric Y. Chou, Bing J. Sheu, Steve H. Jen:
A compact VLSI design for recursive neural networks with hardware annealing capability. ICNN 1995: 1650-1655 - [c23]Bing J. Sheu, Sa Hyun Bang, Wai-Chi Fang:
VLSI Design of Cellular Neutral Networks with Annealing and Optical Input Capabilities. ISCAS 1995: 653-656 - [c22]Bing J. Sheu, Robert C. Chang, Tony H. Wu, Sa Hyun Bang:
VLSI-Compatible Cellular Neural Networks with Optimal Solution Capability for Optimization. ISCAS 1995: 1165-1168 - [c21]Bing J. Sheu, Theodore W. Berger, Tony H. Wu, Richard H. Tsai:
VLSI Neural Network Implementation of a Hippocampal Model. ISCAS 1995: 1664-1667 - [c20]Bing J. Sheu:
Constructing Intelligent Microsystems with Modular VLSI Networks Design. ISCAS 1995: 2100-2103 - 1994
- [j23]Joongho Choi, Bing J. Sheu, Oscal T.-C. Chen:
A monolithic GaAs receiver for optical interconnect systems. IEEE J. Solid State Circuits 29(3): 328-331 (1994) - [j22]Sudhir M. Gowda, Bing J. Sheu:
BSIM plus: an advanced SPICE model for submicron MOS VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(9): 1166-1170 (1994) - [j21]Oscal T.-C. Chen, Bing J. Sheu, Zhen Zhang:
An adaptive vector quantizer based on the Gold-Washing method for image compression. IEEE Trans. Circuits Syst. Video Technol. 4(2): 143-157 (1994) - [j20]Oscal T.-C. Chen, Bing J. Sheu, Wai-Chi Fang:
Image compression using self-organization networks. IEEE Trans. Circuits Syst. Video Technol. 4(5): 480-489 (1994) - [j19]Wai-Chi Fang, Chi-Yung Chang, Bing J. Sheu, Oscal T.-C. Chen, John C. Curlander:
VLSI systolic binary tree-searched vector quantizer for image compression. IEEE Trans. Very Large Scale Integr. Syst. 2(1): 33-44 (1994) - [j18]Joongho Choi, Bing J. Sheu, Josephine C.-F. Chang:
A Gaussian synapse circuit for analog VLSI neural networks. IEEE Trans. Very Large Scale Integr. Syst. 2(1): 129-133 (1994) - [j17]Sudhir M. Gowda, Bing J. Sheu, Wen-Jay Hsu:
Testing of programmable analog neural network chips. J. VLSI Signal Process. 8(3): 267-282 (1994) - [c19]Robert Chen-Hao Chang, Bing J. Sheu:
An Analog MOS Model for Circuit Simulation and Benchmark Test Results. ISCAS 1994: 311-314 - [c18]Sa Hyun Bang, Bing J. Sheu, Josephine C.-F. Chang:
Search of Optimal Solutions in Multi-Level Neural Networks. ISCAS 1994: 423-426 - [c17]Joongho Choi, Bing J. Sheu, Josephine C.-F. Chang:
A Gaussian Synapse Circuit for Analog VLSI Neural Networks. ISCAS 1994: 483-486 - 1993
- [j16]Ji-Chien Lee, Bing J. Sheu, Wai-Chi Fang, Rama Chellappa:
VLSI neuroprocessors for video motion detection. IEEE Trans. Neural Networks 4(2): 178-191 (1993) - [j15]Joongho Choi, Sa Hyun Bang, Bing J. Sheu:
A programmable analog VLSI neural network processor for communication receivers. IEEE Trans. Neural Networks 4(3): 484-495 (1993) - [j14]Bang W. Lee, Bing J. Sheu:
Paralleled hardware annealing for optimal solutions on electronic neural networks. IEEE Trans. Neural Networks 4(4): 588-599 (1993) - [j13]Ji-Chien Lee, Bing J. Sheu, Rama Chellappa:
A VLSI neuroprocessor for image restoration using analog computing-based systolic architecture. J. VLSI Signal Process. 5(2-3): 185-199 (1993) - [j12]Ji-Chien Lee, Bing J. Sheu, Rama Chellappa:
A mixed-signal VLSI competitive neuroprocessor for video motion detection. J. VLSI Signal Process. 6(1): 57-66 (1993) - 1992
- [j11]Oscal T.-C. Chen, Bing J. Sheu, Wai-Chi Fang:
Image Compression on a VLSI Neural-Based Vector Quantizer. Inf. Process. Manag. 28(6): 687-706 (1992) - [j10]Ji-Chien Lee, Bing J. Sheu, Joongho Choi, Ramalingam Chellappa:
A mixed-signal VLSI neuroprocessor for image restoration. IEEE Trans. Circuits Syst. Video Technol. 2(3): 319-324 (1992) - [j9]Wai-Chi Fang, Bing J. Sheu, Oscal T.-C. Chen, Joongho Choi:
A VLSI neural processor for image data compression using self-organization networks. IEEE Trans. Neural Networks 3(3): 506-518 (1992) - [c16]Oscal T.-C. Chen, Zhen Zhang, Bing J. Sheu:
An Adaptive High-Speed Lossy Data Compression. Data Compression Conference 1992: 349-358 - [c15]Oscal T.-C. Chen, Bing J. Sheu, Wai-Chi Fang:
Adaptive vector quantizer for image compression using self-organization approach. ICASSP 1992: 385-388 - [c14]Chia-Fen Chang, Bing J. Sheu, Hiroto Okada:
Design of a multiprocessor DSP chip for flexible information processing. ICASSP 1992: 637-640 - 1991
- [j8]Bang W. Lee, Bing J. Sheu:
Modified Hopfield neural networks for retrieving the optimal solution. IEEE Trans. Neural Networks 2(1): 137-142 (1991) - [c13]Wai-Chi Fang, Bing J. Sheu, Oscal T.-C. Chen:
A Neural Network Based VLSI Vector Quantizer for Real-Time Image Compression. Data Compression Conference 1991: 342-351 - [c12]Bing J. Sheu, Wai-Chi Fang:
Real-time high-ratio image compression using adaptive VLSI neuroprocessors. ICASSP 1991: 1173-1176 - [c11]Wai-Chi Fang, Bing J. Sheu, Ji-Chien Lee:
A VLSI neuroprocessor for real-time image flow computing. ICASSP 1991: 2413-2416 - [c10]Wen-Jay Hsu, Bing J. Sheu, Sudhir M. Gowda:
Testing of Analog Neural Array-Processor Chips. ICCD 1991: 118-121 - [c9]Joongho Choi, Bing J. Sheu:
A GaAs Receiver Module for Optoelectronic Computing and Interconnection. ICCD 1991: 494-497 - 1990
- [c8]David J. Chen, Bing J. Sheu:
Automatic layout generation for mixed analog-digital VLSI neural chips. ICCD 1990: 29-32 - [c7]Wai-Chi Fang, Bing J. Sheu, Ji-Chien Lee:
Real-time computing of optical flow using adaptive VLSI neuroprocessors. ICCD 1990: 122-125 - [c6]Ji-Chien Lee, Bing J. Sheu:
Parallel digital image restoration using adaptive VLSI neural chips. ICCD 1990: 126-129 - [c5]Bang W. Lee, Ji-Chien Lee, Bing J. Sheu:
VLSI image processor using analog programmable synapses and neurons. IJCNN 1990: 575-580
1980 – 1989
- 1989
- [j7]Bing J. Sheu, Wen-Jay Hsu, Bang W. Lee:
An integrated-circuit reliability simulator-RELY. IEEE J. Solid State Circuits 24(2): 473-477 (1989) - [j6]Bang W. Lee, Bing J. Sheu:
Design of a neural-based A/D converter using modified Hopfield network. IEEE J. Solid State Circuits 24(4): 1129-1135 (1989) - [j5]Chung-Ping Wan, Bing J. Sheu:
Temperature dependence modeling for MOS VLSI circuit simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(10): 1065-1073 (1989) - [c4]David J. Chen, Ji-Chien Lee, Bing J. Sheu:
SLAM: a smart analog module layout generator for mixed analog-digital VLSI design. ICCD 1989: 24-27 - [c3]Wen-Jay Hsu, Bing J. Sheu, Vance C. Tyree:
Digital and analog integrated-circuit design with built-in reliability. ICCD 1989: 496-499 - 1988
- [j4]Chih-Ching Shih, Bing J. Sheu, Huy M. Le:
Characterization of GaAs MESFET gate capacitances. IEEE J. Solid State Circuits 23(3): 878-880 (1988) - [j3]Bing J. Sheu, Wen-Jay Hsu, P. K. Ko:
An MOS transistor charge model for VLSI design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(4): 520-527 (1988) - [j2]Chung-Ping Wan, Bing J. Sheu, Shih-Lien Lu:
Device and circuit simulation interface for an integrated VLSI design environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(9): 998-1004 (1988) - [c2]Antony H. Fung, David J. Chen, Ying-Nan Lai, Bing J. Sheu:
Knowledge-based analog circuit synthesis with flexible architecture. ICCD 1988: 48-51 - [c1]Bang W. Lee, Bing J. Sheu:
An investigation on local minima of a Hopfield network for optimization circuits. ICNN 1988: 45-51 - 1987
- [j1]M. C. Hsu, Bing J. Sheu:
Inverse-Geometry Dependence of MOS Transistor Electrical Parameters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(4): 582-585 (1987)
Coauthor Index
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