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ORCIDICCD 1990: Cambridge, MA, USA
- Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 1990, Cambridge, MA, USA, 17-19 September, 1990. IEEE Computer Society 1990, ISBN 0-8186-2079-X
- C. Bernard Shung, Paul H. Siegel, Hemant K. Thapar, Razmik Karabed:
Design issues of a rate 8/10 matched-spectral-null trellis code chip for partial response channels. - Ramesh S. Iyer:
BiCMOS design overview and implementation methodology. 3-6 - B. Bastani, M. Biswal, Ali Iranmanesh, C. Lage, L. Bouknight, Vida Ilderem, A. Solheim, W. Burger, R. Lahri, J. Small:
Submicron BiCMOS technologies for supercomputer and high speed system implementation. 7-10 - T. Fletcher, E. Hahn, J. West:
BiCMOS Futurebus transceiver. 11-13 - Toyohiko Yoshida, Masahito Matsuo, Tatsuya Ueda, Yuichi Saito:
A strategy for avoiding pipeline interlock delays in a microprocessor. 14-19 - Sriram Vajapeyam, Gurindar S. Sohi, Wei-Chung Hsu:
Exploitation of operation-level parallelism in a processor of the CRAY X-MP. 20-23 - Masaki Hashizume, Takeomi Tamesada, Koji Nii:
A parameter adjustment method for analog circuits based on convex fuzzy decision using constraints of satisfactory level. 24-28 - David J. Chen, Bing J. Sheu:
Automatic layout generation for mixed analog-digital VLSI neural chips. 29-32 - Ertugrul Berkcan:
MxSICO: a silicon compiler for mixed analog digital circuits. 33-36 - H.-C. Shih, Predrag G. Kovijanic, Rahul Razdan:
A global feedback detection algorithm for VLSI circuits. 37-40 - Damu Radhakrishnan, Taejin Pyon:
Fault tolerance in RNS: an efficient approach. 41-44 - Patrick C. McGeer, Robert K. Brayton:
The observability don't-care set and its approximations. 45-48 - C. George Hsi, Stuart G. Tucker:
Figures of merit for system path time estimation. 49-55 - Dick W. Harberts, Dré A. J. M. van den Elshout, Harry J. M. Veendrick:
Design for routability of a high-density gate array. 56-59 - Gnanasekaran Swaminathan, James H. Aylor, Barry W. Johnson:
Concurrent testing of VLSI circuits using conservative logic. 60-65 - Andrew L. Reibman:
Reliability analysis of a computer system for a data collection application. 66-69 - Joydeep Ghosh, Anujan Varma:
Reliable design of multichip nonblocking crossbars. 70-73 - Ellen E. Witte, Roger D. Chamberlain, Mark A. Franklin:
Task assignment by parallel simulated annealing. 74-77 - Fillia Makedon, Adonios Simvonis:
Fast parallel communication on mesh connected machines with low buffer requirements. 78-81 - Caroline Benveniste, Yarsun Hsu:
A trace-driven analysis of the 'wrap-around' network. 82-85 - Hiroshi Nakada, Naoya Sakurai, Yukiharu Kanayama, Naohisa Ohta, Kiyoshi Oguri:
Vector processor design for parallel DSP systems using hierarchical behavioral description based synthesizer. 86-89 - Hiroto Yasuura, Nagisa Ishiura:
Formal semantics of UDL/I and its applications to CAD/DA tools. 90-94 - Yasushi Koseko, C. Hiramine, Takuji Ogihara, Shinichi Murai:
Rule-based testability rule check program. 95-98 - Hiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko Tanaka:
Practical design assistance at register transfer level using a data path verifier. 99-102 - Niraj K. Jha, Carol Q. Tong:
Design of robustly testable static CMOS parity trees derived from binary decision diagrams. 103-106 - Gueesang Lee, Mary Jane Irwin, Robert Michael Owens:
Test generation in circuits constructed by input decomposition. 107-111 - Chin-Long Wey, Jyhyeung Ding:
Design of repairable and fully testable folded PLAs. 112-115 - Pradip Bose, Subir Bandyopadhyay, D. Dutta Majumder:
Synthesis of testable PLAs using adaptive heuristics for efficiency. 116-120 - Wai-Chi Fang, Bing J. Sheu, Ji-Chien Lee:
Real-time computing of optical flow using adaptive VLSI neuroprocessors. 122-125 - Ji-Chien Lee, Bing J. Sheu:
Parallel digital image restoration using adaptive VLSI neural chips. 126-129 - Scott E. Ritter, K. Soumyanath:
An analog parallel distributed solution to the shortest path problem. 130-134 - Marcus S. Yoo, Arding Hsu:
DEBBIE: a configurable user interface for CAD frameworks. 135-140 - Michael Koster, Martin Geiger, Peter Duzy:
ASIC design using the high-level synthesis system CALLAS: a case study. 141-146 - Sailesh K. Rao, Mehdi Hatamian, Bryan D. Ackland:
A design environment for high performance VLSI signal processing. 147-152 - James H. Aylor, James P. Cohoon, E. L. Feldhousen, Barry W. Johnson:
Compacting randomly generated test sets. 153-156 - D. Michael Miller, Shujian Zhang, Werner Pries, Robert D. McLeod:
Estimating aliasing in CA and LFSR based signature registers. 157-160 - Franc Brglez, Clay S. Gloster Jr., Gershon Kedem:
Built-in self-test with weighted random pattern hardware. 161-166 - Shigeru Takasaki, Nobuyoshi Nomizu, Yoshihiro Hirabayashi, Hiroshi Ishikura, Masahiro Kurashita, Nobuhiko Koike, Toshiyuki Nakata:
HAL III: function level hardware logic simulation. 167-170 - Young-Hyun Jun, Ibrahim N. Hajj, Sang-Heon Lee, Song-Bai Park:
High speed VLSI logic simulation using bitwise operations and parallel processing. 171-174 - David T. Blaauw, Prithviraj Banerjee, Jacob A. Abraham:
Automatic classification of node types in switch-level descriptions. 175-178 - Brad Martin, Steve McMahan, Lal Sood:
68040 memory modules and bus controller. 179-182 - Kirk Holden, Renny Eisele, Mike Kobe, James Raleigh, Thomas Spohrer:
68040 integer module. 183-186 - Shawn McCloud, Donnie Anderson, Chris DeWitt, Chris Hinds, Ying-Wai Ho, Danny Marquette, Eric Quintana:
A floating point unit for the 68040. 187-190 - Thomas Spohrer, Danny Marquette, Michael Gallup:
Test architecture of the Motorola 68040. 191-194 - Sandeep Aranake, Anil Dikshit, A. Arun:
An edge based netlist extractor for IC layouts. 195-200 - Hansruedi Heeb, Albert E. Ruehli:
Approximate time-domain models of three-dimensional interconnects. 201-205 - W. De Rammelaere, Ivo Bolsens, Luc J. M. Claesen, Hugo De Man:
Derivation of signal flow direction in MOS VLSI: an alternative. 206-209 - Jack Keil Wolf:
Digital magnetic recording systems. 210-213 - Philip S. Bednarz, William L. Abbott, Kevin D. Fisher, John M. Cioffi:
Complexity issues in RAM-DFE design for magnetic disk drives. 215-219 - Shinji Kimura, Edmund M. Clarke:
A parallel algorithm for constructing binary decision diagrams. 220-223 - Christian Berthet, Olivier Coudert, Jean Christophe Madre:
New ideas on symbolic manipulations of finite state machines. 224-227 - Paul Loewenstein, David L. Dill:
Formal verification of cache systems using refinement relations. 228-233 - Hartmut C. Ritter, Thomas M. Schwair:
Modular BIST concept for microprocessors. 234-237 - Suresh K. Gopalakrishnan, Gary K. Maki:
VLSI asynchronous sequential circuit design. 238-242 - Ramachandra P. Kunda, Bharat Deep Rathi:
A functional diagnostics methodology. 243-246 - King Fai Pang:
Architectures for pipelined Wallace tree multiplier-accumulators. 247-250 - Zhi-Jian Mou, Francis Jutand:
A class of close-to-optimum adder trees allowing regular and compact layout. 251-254 - Akhilesh Tyagi:
A reduced area scheme for carry-select adders. 255-258 - N. Hendrickson, R. Langer, T. Coe, M. Vana, I. Deyhimy:
2.5 Gbits/sec telecommunications gate array. 259-262 - G. Taylor, G. Sanguinetti, R. Lane:
An approach to 150 K gate low power ECL cell based integrated circuits. 263-268 - Patrick Lampin, J. C. Le Garrec, C. Marion, J. P. Mifsud, T. Mille, S. Nicot, B. Rousseau, R. Saura, T. Tatry, C. John Glossner, R. D. Kilmoyer:
Design and application trade-offs between high-density and high-speed ASICs. 269-272 - Pranav Ashar, Srinivas Devadas, A. Richard Newton:
Testability driven synthesis of interacting finite state machines. 273-276 - Abhijit Ghosh, Srinivas Devadas, A. Richard Newton:
Heuristic minimization of Boolean relations using testing techniques. 277-281 - Johnson Chan Limqueco, Saburo Muroga:
SYLON-REDUCE: an MOS network optimization algorithms using permissible functions. 282-285 - Hitomi Sato, Norikazu Takahashi, Yusuke Matsunaga, Masahiro Fujita:
Boolean technology mapping for both ECI and CMOS circuits based on permissible functions and binary decision diagrams. 286-290 - Daniel G. Saab, Robert B. Mueller-Thuns, David T. Blaauw, Joseph T. Rahmeh, Jacob A. Abraham:
Fault grading of large digital systems. 290-293 - Marc E. Levitt, Kaushik Roy, Jacob A. Abraham:
BiCMOS fault models: is stuck-at adequate? 294-297 - Silvano Gai, Pier Luca Montessoro:
The fault dropping problem in concurrent event driven simulation. 298-301 - O. C. McNally, John V. McCanny, Roger F. Woods:
Optimized bit level architectures for IIR filtering. 302-306 - Ulrich Schmidt, Sönke Mehrgardt:
Wavefront array processor for video applications. 307-310 - P. J. Rose, B. G. Koether:
A 75 MHz CMOS digital convolver. 311-314 - Sanjay Nichani, N. Ranganathan:
SAP: design of a systolic array processor for computation in vision. 315-318 - M. Mahmood, Farhad Mavaddat, M. I. Elmastry:
Experiments with an efficient heuristic algorithm for local microcode generation. 319-323 - Ching-Yi Wang, Keshab K. Parhi:
Automatic generation of control circuits in pipelined DSP architectures. 324-327 - Stefaan Note, Francky Catthoor, Gert Goossens, Hugo De Man:
Combined hardware selection and pipelining in high performance data-path design. 328-331 - Massoud Pedram, Bryan Preas:
A hierarchical floorplanning approach. 332-338 - Malgorzata Marek-Sadowska, Shen P. Lin:
Pin assignment for improved performance in standard cell design. 339-342 - Howard H. Chen:
Pseudo pin assignment for single-layer over-the-cell routing. 343-346 - Akira Katsuno, Hiromasa Takahashi, Hajime Kubosawa, Tomio Sato, Atsuhiro Suga, Gensuke Goto:
A 64-bit floating-point processing unit with a horizontal instruction code for parallel operations. 347-350 - Gideon D. Intrater, Dan Biran:
Application specific microprocessor [NS3200/EP family]. 351-354 - Hiroshi Nakashima, Yasutaka Takeda, Katsuto Nakajima, Hideki Andou, Kiyohiro Furutani:
A pipelined microprocessor for logic programming languages. 355-359 - Marek A. Perkowski, Malgorzata Chrzanowska-Jeske, Tuhar Shah:
Minimization of multioutput TANT networks for unlimited fan-in network model. 360-363 - TingTing Hwang, Robert Michael Owens, Mary Jane Irwin:
Logic synthesis for programmable logic devices. 364-367 - Devadas Varma, Eliezer A. Trachtenberg:
On the estimation of logic complexity for design automation applications. 368-371 - J. M. Saul:
An improved algorithm for the minimization of mixed polarity Reed-Muller representations. 372-375 - Chung-Han Chen, Nian-Feng Tzeng:
An area-efficient reconfigurable binary tree architecture. 376-379 - Tom Leighton, Derek Linsinski, Bruce M. Maggs:
Empirical evaluation of randomly-wire multistage networks. 380-385 - David L. Allen, Richard Goldenberg:
Design aids and test results for laser-programmable logic arrays. 386-390 - Dwight D. Hill, Daniel R. Cassiday:
Preliminary description of Tabula Rasa, an electrically reconfigurable hardware engine. 391-395 - Teofilo F. Gonzalez, Si-Qing Zheng:
Multiterminal-net routing by grid stretching. 396-399 - Sridhar Krishnamurthy, Joseph F. JáJá:
An efficient parallel algorithm for channel routing. 400-403 - Ralph H. J. M. Otten, Lukas P. P. P. van Ginneken:
The complexity of adaptive annealing. 404-407 - Kien A. Hua, A. Hunt, L. Liu, J.-K. Peir, D. Pruett, J. Temple:
Early resolution of address translation in cache design. 408-412 - M. Morioka, K. Kurita, H. Kobayashi, H. Sawamoto:
Cache design for high performance computers with BiCMOS VLSIs. 413-416 - Hideto Niijima, Nobuyuki Oba:
QRAM-Quick access memory system. 417-420 - Oskar Kowarik, Rainer Kraus, Kurt Hoffmann, Karl H. Horninger:
Associative and data processing Mbit-DRAM. 421-424 - Takao Matsumoto, Toshikazu Sakano, Kazuhiro Noguchi, Tomoko Sawabe:
Computer systems employing reconfigurable board-to-board free-space optical interconnections: COSINE-1 and -2. 426-429 - Kevin Lam, Larry R. Dennison, William J. Dally:
Simultaneous bidirectional signalling for IC systems. 430-433 - C. G. Lin-Hendel:
Accurate interconnect modeling for high frequency LSI/VLSI circuits and systems. 434-442 - Jerzy W. Rozenblit, John L. Prince, Olgierd A. Palusinski:
Towards a VLSI packaging design support environment (PDSE); concepts and implementation. 443-448 - Po-Yang F. Lin, Kazuo Nakajima:
A linear time algorithm for optimal CMOS functional cell layouts. 449-453 - Dwight D. Hill, Marw A. Aranha, Donald D. Shugard:
Placement algorithms for CMOS cell synthesis. 454-458 - Arun Rajanala, Akhilesh Tyagi:
An area estimation technique for module generation. 459-462 - F. Warren Shih, Tze Chiang Lee, Shauchi Ong:
A file-based adaptive prefetch caching design. 463-466 - Jean-Luc Peter:
Design of a custom processing unit based on Intel i486 architectures and performances trade-offs. 467-470 - Kwangkeun Yi, Luddy Harrison:
On-the-fly circuit to measure the average working set size. 471-474
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