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ORCIDYoshiharu Aimoto
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2010 – 2019
- 2011
[j7]Koichi Takeda, Toshio Saito, Shinobu Asayama, Yoshiharu Aimoto, Hiroyuki Kobatake, Shinya Ito, Toshifumi Takahashi, Masahiro Nomura, Kiyoshi Takeuchi, Yoshihiro Hayashi
:
Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMs. IEEE J. Solid State Circuits 46(4): 806-814 (2011)
2000 – 2009
- 2006
- [j6]Koichi Takeda, Yasuhiko Hagihara, Yoshiharu Aimoto, Masahiro Nomura, Yoetsu Nakazawa, Toshio Ishii, Hiroyuki Kobatake:
A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications. IEEE J. Solid State Circuits 41(1): 113-121 (2006) - [j5]Masahiro Nomura, Yoshifumi Ikenaga, Koichi Takeda, Yoetsu Nakazawa, Yoshiharu Aimoto, Yasuhiko Hagihara:
Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes. IEEE J. Solid State Circuits 41(4): 805-814 (2006) - 2001
- [j4]Kenji Noda, Koichi Takeda, Koujirou Matsui, Shinya Ito, Sadaaki Masuoka, Hideaki Kawamoto, Nobuyuki Ikezawa, Yoshiharu Aimoto, Noritsugu Nakamura, Takahiro Iwasaki, Hideo Toyoshima, Tadahiko Horiuchi:
An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield. IEEE J. Solid State Circuits 36(3): 510-515 (2001) - 2000
- [j3]Koichi Takeda, Yoshiharu Aimoto, Noritsugu Nakamura, Hideo Toyoshima, Takahiro Iwasaki, Kenji Noda, Koujirou Matsui, Shinya Itoh, Sadaaki Masuoka, Tadahiko Horiuchi, Atsushi Nakagawa, Kenju Shimogawa, Hiroyuki Takahashi:
A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro. IEEE J. Solid State Circuits 35(11): 1631-1640 (2000) - [c2]Kenji Noda, Koujirou Matsui, Shinya Ito, Sadaaki Masuoka, Hiroyuki Kawamoto, Nobuyuki Ikezawa, Koichi Takeda, Yoshiharu Aimoto, Naoto Nakamura, Hideo Toyoshima, Takahiro Iwasaki, Tadahiko Horiuchi:
An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shield. CICC 2000: 283-286
1990 – 1999
- 1998
- [c1]Masato Motomura, Yoshiharu Aimoto, Atsufkni Shibayama, Yoshikazu Yabe, Masakazu Yamashina:
An Embedded DRAM-FPGA Chip with Instantaneous Logic Reconfiguration. FCCM 1998: 264-266 - 1995
- [j2]Tohru Kimura, Kazuyuki Nakamura, Yoshiharu Aimoto, Takashi Manabe, Nobuyuki Yamashita, Yoshihiro Fujita, Shin'ichiro Okazaki, Masakazu Yamashina:
Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array processor applications. IEEE J. Solid State Circuits 30(6): 637-643 (1995) - 1994
- [j1]Nobuyuki Yamashita, Tohru Kimura, Yoshihiro Fujita, Yoshiharu Aimoto, Takashi Manabe, Shin'ichiro Okazaki, Kazuyuki Nakamura, Masakazu Yamashina:
A 3.84 GIPS integrated memory array processor with 64 processing elements and a 2-Mb SRAM. IEEE J. Solid State Circuits 29(11): 1336-1343 (1994)
Coauthor Index
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