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2020 – today
- 2023
[c11]Minwoo Kang, Azade Nova, Eshan Singh, Geetheeka Sharron Bathini, Yuriy Viktorov:
LFPS: Learned Formal Proof Strengthening for Efficient Hardware Verification. ICCAD 2023: 1-9- 2021
- [i4]Karthik Ganesan, Florian Lonsing, Srinivasa Shashank Nuthakki, Eshan Singh, Mohammad Rahmani Fadiheh, Wolfgang Kunz, Dominik Stoffel, Clark W. Barrett, Subhasish Mitra:
Effective Pre-Silicon Verification of Processor Cores by Breaking the Bounds of Symbolic Quick Error Detection. CoRR abs/2106.10392 (2021) - 2020
- [c10]Eshan Singh, Florian Lonsing, Saranyu Chattopadhyay
, Maxwell Strange, Peng Wei, Xiaofan Zhang, Yuan Zhou, Deming Chen, Jason Cong, Priyanka Raina, Zhiru Zhang, Clark W. Barrett, Subhasish Mitra:
A-QED Verification of Hardware Accelerators. DAC 2020: 1-6 - [c9]Keerthikumara Devarajegowda, Mohammad Rahmani Fadiheh, Eshan Singh, Clark W. Barrett, Subhasish Mitra, Wolfgang Ecker, Dominik Stoffel, Wolfgang Kunz:
Gap-free Processor Verification by S2QED and Property Generation. DATE 2020: 526-531
2010 – 2019
- 2019
- [c8]Eshan Singh, Keerthikumara Devarajegowda, Sebastian Simon, Ralf Schnieder, Karthik Ganesan, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz, Clark W. Barrett, Wolfgang Ecker, Subhasish Mitra:
Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study. DATE 2019: 1000-1005 - [c7]Florian Lonsing, Karthik Ganesan, Makai Mann, Srinivasa Shashank Nuthakki, Eshan Singh, Mario Srouji, Yahan Yang, Subhasish Mitra, Clark W. Barrett:
Unlocking the Power of Formal Hardware Verification with CoSA and Symbolic QED: Invited Paper. ICCAD 2019: 1-8 - [i3]Eshan Singh, Keerthikumara Devarajegowda, Sebastian Simon, Ralf Schnieder, Karthik Ganesan, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz, Clark W. Barrett, Wolfgang Ecker, Subhasish Mitra:
Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study. CoRR abs/1902.01494 (2019) - 2017
- [c6]Eshan Singh, Clark W. Barrett, Subhasish Mitra:
E-QED: Electrical Bug Localization During Post-silicon Validation Enabled by Quick Error Detection and Formal Methods. CAV (2) 2017: 104-125 - [i2]Eshan Singh, Clark W. Barrett, Subhasish Mitra:
E-QED: Electrical Bug Localization During Post-Silicon Validation Enabled by Quick Error Detection and Formal Methods. CoRR abs/1707.07671 (2017) - [i1]Eshan Singh, David Lin, Clark W. Barrett, Subhasish Mitra:
Logic Bug Detection and Localization Using Symbolic Quick Error Detection. CoRR abs/1711.06541 (2017) - 2016
- [j1]Eshan Singh, David Lin, Clark W. Barrett, Subhasish Mitra:
Symbolic Quick Error Detection for Pre-Silicon and Post-Silicon Validation: Frequently Asked Questions. IEEE Des. Test 33(6): 55-62 (2016) - 2015
- [c5]David Lin, Eshan Singh, Clark W. Barrett, Subhasish Mitra:
A structured approach to post-silicon validation and debug using symbolic quick error detection. ITC 2015: 1-10 - 2014
- [c4]Eshan Singh:
Analytical Modeling of 3D Stacked IC Yield from Wafer to Wafer Stacking with Radial Defect Clustering. VLSID 2014: 26-31 - [c3]Eshan Singh:
Modeling location based wafer die yield variation in estimating 3D stacked IC yield from wafer to wafer stacking. VTS 2014: 1-6 - 2012
- [c2]Eshan Singh:
Impact of Radial defect clustering on 3D stacked IC yield from wafer to wafer stacking. ITC 2012: 1-7 - 2011
- [c1]Eshan Singh:
Exploiting rotational symmetries for improved stacked yields in W2W 3D-SICs. VTS 2011: 32-37
Coauthor Index
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