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ORCIDThomas Byunghak Cho
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2020 – today
- 2022
[j12]Venumadhav Bhagavatula
, Fan Zhang, Che-Chun Kuo, Anirban Sarkar, Ashutosh Verma, Tienyu Chang, Xiaohua Yu, Daeyoung Yoon, Ivan Siu-Chuang Lu, Sang Won Son, Thomas Byunghak Cho:
A 5G FR2 Power-Amplifier With an Integrated Power-Detector for Closed-Loop EIRP Control. IEEE J. Solid State Circuits 57(5): 1257-1266 (2022)- [c24]Jun-Suk Bang, Dong-Su Kim, Jeongkwang Lee, Sung-Youb Jung, Young-Hwan Choo, Seungchan Park, Young-Ho Jung, Jae-Young Ko, Takahiro Norniyama, Jongbeom Baek, Jae-Yeol Han, Sang-Han Lee, Ik-Hwan Kim, Ji-Seon Paek, Jongwoo Lee, Thomas Byunghak Cho:
2-Tx Digital Envelope-Tracking Supply Modulator Achieving 200MHz Channel Bandwidth and 93.6% Efficiency for 2G/3G/LTE/NR RF Power Amplifiers. ISSCC 2022: 1-3 - [c23]Ashutosh Verma, Venumadhav Bhagavatula, Amitoj Singh, Wanghua Wu, Hariharan Nagarajan, Pak-Kim Lau, Xiaohua Yu, Omar Elsayed, Ajaypat Jain, Anirban Sarkar, Fan Zhang, Che-Chun Kuo, Patrick McElwee, Pei-Yuan Chiang, Chengkai Guo, Zhanjun Bai, Tienyu Chang, Abishek Mann, Andreas Rydin, Xingliang Zhao, Jeiyoung Lee, Daeyoung Yoon, Chih-Wei Yao, Siuchuang-Ivan Lu, Sang Won Son, Thomas Byunghak Cho:
A 16-Channel, 28/39GHz Dual-Polarized 5G FR2 Phased-Array Transceiver IC with a Quad-Stream IF Transceiver Supporting Non-Contiguous Carrier Aggregation up to 1.6GHz BW. ISSCC 2022: 1-3 - [c22]Jaehong Jung, Seunghyun Oh, Joo-Myoung Kim, Gihyeok Ha, Jinhyeon Lee, Seungjin Kim, Euiyoung Park, Jaehoon Lee, Yelim Yoon, Seungyong Bae, Wonkang Kim, Yong Lim, Kyungsoo Lee, Junho Huh, Jongwoo Lee, Thomas Byunghak Cho:
A Single-Crystal-Oscillator-Based Clock-Management IC with 18× Start-Up Time Reduction and 0.68ppm/ºC Duty-Cycled Machine-Learning-Based RCO Calibration. ISSCC 2022: 58-60 - [c21]Barosaim Sung, Hyun-Gi Seok, Jaekwon Kim, Jaehoon Lee, Taejin Jang, Ilhoon Jang, Youngmin Kim, Anna Yu, Jong-Hyun Jang, Jiyoung Lee, Jeongyeol Bae, Euiyoung Park, Sung-Jun Lee, Seokwon Lee, Joohan Kim, Beomkon Kim, Yong Lim, Seunghyun Oh, Jongwoo Lee, Thomas Byunghak Cho, Inyup Kang:
A Single-Path Digital-IF Receiver Supporting Inter/Intra 5-CA with a Single Integer LO-PLL in 14nm CMOS FinFET. ISSCC 2022: 440-442 - 2021
- [j11]Wanghua Wu, Chih-Wei Yao, Chengkai Guo, Pei-Yuan Chiang, Lei Chen, Pak-Kim Lau, Zhanjun Bai, Sang Won Son, Thomas Byunghak Cho:
A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO. IEEE J. Solid State Circuits 56(12): 3756-3767 (2021) - [c20]Jongsoo Lee, Byoungjoong Kang, Seongwon Joo, Seokwon Lee, Joongho Lee, Seunghoon Kang, Ikkyun Jo, Suseop Ahn, Jaeseung Lee, Jeongyeol Bae, Won Ko, Woniun Jung, Sangho Lee, Sangsung Lee, Euiyoung Park, Sungiun Lee, Jeongkyun Woo, Jaehoon Lee, Yanghoon Lee, Kyungmin Lee, Jongwoo Lee, Thomas Byunghak Cho, Inyup Kang:
6.1 A Low-Power and Low-Cost 14nm FinFET RFIC Supporting Legacy Cellular and 5G FR1. ISSCC 2021: 90-92 - [c19]Wanghua Wu, Chih-Wei Yao, Chengkai Guo, Pei-Yuan Chiang, Pak-Kim Lau, Lei Chen, Sang Won Son, Thomas Byunghak Cho:
32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels. ISSCC 2021: 444-446 - [c18]Dongsu Kim, Jun-Suk Bang, Jongbeom Baek, Seungchan Park, Young-Ho Jung, Jae-Yeol Han, Ik-Hwan Kim, Sung-Youb Jung, Takahiro Nomiyama, Ji-Seon Paek, Jongwoo Lee, Thomas Byunghak Cho:
33.9 A Hybrid Switching Supply Modulator Achieving 130MHz Envelope-Tracking Bandwidth and 10W Output Power for 2G/3G/LTE/NR RF Power Amplifiers. ISSCC 2021: 476-478 - 2020
- [j10]Jongsoo Lee, Jae-Yeol Han, Chilun Lo, Jongmi Lee, Wan Kim, Seungjin Kim, Byoungjoong Kang, Juyoung Han, Sangdon Jung, Takahiro Nomiyama, Jongwoo Lee, Thomas Byunghak Cho, Inyup Kang:
NB-IoT and GNSS All-In-One System-On-Chip Integrating RF Transceiver, 23-dBm CMOS Power Amplifier, Power Management Unit, and Clock Management System for Low Cost Solution. IEEE J. Solid State Circuits 55(12): 3400-3413 (2020) - [c17]Jongbeom Baek, Takahiro Nomiyama, Seungchan Park, Young-Ho Jung, Dongsu Kim, Jae-Yeol Han, Jun-Suk Bang, Yumi Lee, Ik-Hwan Kim, Ji-Seon Paek, Jongwoo Lee, Thomas Byunghak Cho:
11.7 A Voltage-Tolerant Three-Level Buck-Boost DC-DC Converter with Continuous Transfer Current and Flying Capacitor Soft Charger Achieving 96.8% Power Efficiency and 0.87µs/V DVS Rate. ISSCC 2020: 202-204 - [c16]Jongsoo Lee, Jae-Yeol Han, Chilun Lo, Jongmi Lee, Wan Kim, Seungjin Kim, Byoungjoong Kang, Juyoung Han, Sangdon Jung, Takahiro Nomiyama, Jongwoo Lee, Thomas Byunghak Cho, Inyup Kang:
30.2 NB-IoT and GNSS All-in-One System-on-Chip Integrating RF Transceiver, 23dBm CMOS Power Amplifier, Power Management Unit and Clock Management System for Low-Cost Solution. ISSCC 2020: 462-464 - [c15]Sangwook Han, Jaehyuk Jang, Jaeseung Lee, Daechul Jeong, Joonhee Lee, Jongsoo Lee, Chung Lau, Juyoung Han, Sung-Jun Lee, Jeongyeol Bae, Ikkyun Cho, Sang-Yun Lee, Shinwoong Kim, Jae Hoon Lee, Yanghoon Lee, Jaehong Jung, Junho Huh, Jongwoo Lee, Thomas Byunghak Cho, Inyup Kang:
An RF Transceiver with Full Digital Interface Supporting 5G New Radio FR1 with 3.84Gbps DL/1.92Gbps UL and Dual-Band GNSS in 14nm FinFET CMOS. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j9]Wanghua Wu, Chih-Wei Yao, Kunal Godbole, Ronghua Ni, Pei-Yuan Chiang, Yongping Han, Yongrong Zuo, Ashutosh Verma, Ivan Siu-Chuang Lu, Sang Won Son, Thomas Byunghak Cho:
A 28-nm 75-fsrms Analog Fractional- $N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction. IEEE J. Solid State Circuits 54(5): 1254-1265 (2019) - [j8]Jongwoo Lee, Kiyong Son, Hyungsun Lim, Daechul Jeong, Ilyong Jong, Sanghyun Baek, Jae Hoon Lee, Ronghua Ni, Yongrong Zuo, Chih-Wei Yao, Seungchan Heo, Sangwook Han, Thomas Byunghak Cho, Inyup Kang, Joonhee Lee, Byoungjoong Kang, Jeongyeol Bae, Jaehyuk Jang, Seunghyun Oh, Ji-Soo Chang, Sanghoon Kang:
A Sub-6-GHz 5G New Radio RF Transceiver Supporting EN-DC With 3.15-Gb/s DL and 1.27-Gb/s UL in 14-nm FinFET CMOS. IEEE J. Solid State Circuits 54(12): 3541-3552 (2019) - [j7]Jaekwon Kim, Woojin Jang, Yanghoon Lee, Wan Kim, Seunghyun Oh, Jongwoo Lee, Jaehyuk Choi, Jung-Hoon Chun, Thomas Byunghak Cho:
Design and Analysis of a 12-b Current-Steering DAC in a 14-nm FinFET Technology for 2G/3G/4G Cellular Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(10): 3723-3732 (2019) - [c14]Ji-Seon Paek, Dong-Su Kim, Jun-Suk Bang, Jongbeom Baek, Jeong-Hyun Choi, Takahiro Nomiyama, Jae-Yeol Han, Young-Hwan Choo, Yong-Sik Youn, Euiyoung Park, Sung-Jun Lee, Ik-Hwan Kim, Jongwoo Lee, Thomas Byunghak Cho, Inyup Kang:
An 88%-Efficiency Supply Modulator Achieving 1.08μs/V Fast Transition and 100MHz Envelope-Tracking Bandwidth for 5G New Radio RF Power Amplifier. ISSCC 2019: 238-240 - [c13]Ji-Seon Paek, Takahiro Nomiyama, Jae-Yeol Han, Ik-Hwan Kim, Yumi Lee, Dongsu Kim, Euiyoung Park, Sung-Jun Lee, Jongwoo Lee, Thomas Byunghak Cho, Inyup Kang:
A 90ns/V Fast-Transition Symbol-Power-Tracking Buck Converter for 5G mm-Wave Phased-Array Transceiver. ISSCC 2019: 240-242 - [c12]Jongwoo Lee, Sangwook Han, Joonhee Lee, Byoungjoong Kang, Jeongyeol Bae, Jaehyuk Jang, Seunghyun Oh, Su-Seob Ahn, Sanghoon Kang, Quang-Diep Bui, Kiyong Son, Hyungsun Lim, Daechul Jeong, Ronghua Ni, Yongrong Zuo, Ilyong Jong, Chih-Wei Yao, Seungchan Heo, Thomas Byunghak Cho, Inyup Kang:
A Sub-6GHz 5G New Radio RF Transceiver Supporting EN-DC with 3.15Gb/s DL and 1.27Gb/s UL in 14nm FinFET CMOS. ISSCC 2019: 354-356 - 2018
- [c11]Jaewon Choi, Nam-Seog Kim, Juyoung Han, Thomas Byunghak Cho:
A 0.46-2.1 GHz Spurious and Oscillator-Pulling Free LO Generator for Cellular NB-IoT Transmitter with 23 dBm Integrated PAs in 28nm CMOS. A-SSCC 2018: 299-302 - [c10]Youngmin Kim, Pilsung Jang, Joongseok Lim, Won Ko, Seungchan Heo, Jongwoo Lee, Thomas Byunghak Cho:
A Ka-band Phase Shifting Low Noise Amplifier with Gain Error Compensation for 5G RF beam forming array using 14nm FinFET CMOS. ISCAS 2018: 1-4 - [c9]Qing Liu, Dae Hyun Kwon, Quang-Diep Bui, Jeong-Hyun Choi, Jaehun Lee, Sanghyun Baek, Seungchan Heo, Thomas Byunghak Cho:
A 1.4-to-2.7GHz high-efficiency RF transmitter with an automatic 3FLO-suppression tracking-notch-filter mixer supporting HPUE in 14nm FinFET CMOS. ISSCC 2018: 172-174 - [c8]Takahiro Nomiyama, Yong-Sik Youn, Young-Hwan Choo, Dong-Su Kim, Jae-Yeol Han, Jun-Hee Jung, Jongbeom Baek, Sung-Jun Lee, Euiyoung Park, Jeong-Hyun Choi, Ji-Seon Paek, Jongwoo Lee, Thomas Byunghak Cho, Inyup Kang:
A 2TX supply modulator for envelope-tracking power amplifier supporting intra- and inter-band uplink carrier aggregation and power class-2 high-power user equipment. ISSCC 2018: 434-436 - 2017
- [j6]Chih-Wei Yao, Ronghua Ni, Chung Lau, Wanghua Wu, Kunal Godbole, Yongrong Zuo, Sangsoo Ko, Nam-Seog Kim, Sangwook Han, Ikkyun Jo, Joonhee Lee, Juyoung Han, Daehyeon Kwon, Chulho Kim, Shinwoong Kim, Sang Won Son, Thomas Byunghak Cho:
A 14-nm 0.14-psrms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration. IEEE J. Solid State Circuits 52(12): 3446-3457 (2017) - [c7]Jongmi Lee, Jongwoo Lee, Chilun Lo, Jaehoon Lee, In-Young Lee, Byungki Han, Seunghyun Oh, Thomas Byunghak Cho:
A reconfigurable analog baseband transformer for multistandard applications in 14nm FinFET CMOS. A-SSCC 2017: 5-8 - [c6]Byungki Han, Jongwoo Lee, Seunghyun Oh, Jae-Kwon Kim, Eswar Mamidala, Thomas Byunghak Cho:
A 14nm FinFET analog baseband SOC for multi-mode cellular applications with tri-band carrier aggregation. ISOCC 2017: 1-2 - [c5]Chih-Wei Yao, Wing Fai Loke, Ronghua Ni, Yongping Han, Haoyang Li, Kunal Godbole, Yongrong Zuo, Sangsoo Ko, Nam-Seog Kim, Sangwook Han, Ikkyun Jo, Joonhee Lee, Juyoung Han, Daehyeon Kwon, Chulho Kim, Shinwoong Kim, Sang Won Son, Thomas Byunghak Cho:
24.8 A 14nm fractional-N digital PLL with 0.14psrms jitter and -78dBc fractional spur for cellular RFICs. ISSCC 2017: 422-423 - 2016
- [j5]Siddharth Seth, Dae Hyun Kwon, Sriramkumar Venugopalan, Sang Won Son, Yongrong Zuo, Venumadhav Bhagavatula, Jaehyun Lim, Dongjin Oh, Thomas Byunghak Cho:
A Dynamically Biased Multiband 2G/3G/4G Cellular Transmitter in 28 nm CMOS. IEEE J. Solid State Circuits 51(5): 1096-1108 (2016) - [j4]Ji-Seon Paek, Seung-Chul Lee, Yong-Sik Youn, Dong-Su Kim, Jeong-Hyun Choi, Jun-Hee Jung, Young-Hwan Choo, Sung-Jun Lee, Jae-Yeol Han, Thomas Byunghak Cho:
A - 137 dBm/Hz Noise, 82% Efficiency AC-Coupled Hybrid Supply Modulator With Integrated Buck-Boost Converter. IEEE J. Solid State Circuits 51(11): 2757-2768 (2016) - [c4]Ji-Seon Paek, Yong-Sik Youn, Jeong-Hyun Choi, Dong-Su Kim, Jun-Hee Jung, Young-Hwan Choo, Sung-Jun Lee, Seung-Chul Lee, Thomas Byunghak Cho, Inyup Kang:
20.7 An RF-PA supply modulator achieving 83% efficiency and -136dBm/Hz noise for LTE-40MHz and GSM 35dBm applications. ISSCC 2016: 354-355 - 2015
- [c3]Seung-Chul Lee, Ji-Seon Paek, Jun-Hee Jung, Yong-Sik Youn, Sung-Jun Lee, Min-Soo Cho, Jae-Jol Han, Jung-Hyun Choi, Yong-Whan Joo, Takahiro Nomiyama, Su-Ho Lee, Il-Young Sohn, Thomas Byunghak Cho, Byeong-Ha Park, Inyup Kang:
2.7 A hybrid supply modulator with 10dB ET operation dynamic range achieving a PAE of 42.6% at 27.0dBm PA output power. ISSCC 2015: 1-3 - [c2]Si-Duk Sung, Sung-Wan Hong, Jun-Suk Bang, Ji-Seon Paek, Seung-Chul Lee, Thomas Byunghak Cho, Gyu-Hyeong Cho:
86.55% Peak efficiency envelope modulator for 1.5W 10MHz LTE PA without AC coupling capacitor. VLSIC 2015: 342- - 2014
- [c1]Jongwoo Lee, Byungki Han, Jae-Hyun Lim, Su-Seob Ahn, Jae-Kwon Kim, Thomas Byunghak Cho:
A reconfigurable analog baseband for single-chip, Saw-less, 2G/3G/4G cellular transceivers with carrier aggregation. A-SSCC 2014: 9-12
2000 – 2009
- 2004
- [j3]Thomas Byunghak Cho, David Kang, Chun-Huat Heng, Bang-Sup Song:
A 2.4-GHz dual-mode 0.18-μm CMOS transceiver for Bluetooth and 802.11b. IEEE J. Solid State Circuits 39(11): 1916-1926 (2004)
1990 – 1999
- 1997
- [j2]Jacques C. Rudell, Jia-Jiunn Ou, Thomas Byunghak Cho, George Chien, Francesco Brianti, Jeffrey A. Weldon, Paul R. Gray:
A 1.9-GHz wide-band IF double conversion CMOS receiver for cordless telephone applications. IEEE J. Solid State Circuits 32(11): 2071-2088 (1997) - 1995
- [j1]Thomas Byunghak Cho, Paul R. Gray:
A 10 b, 20 Msample/s, 35 mW pipeline A/D converter. IEEE J. Solid State Circuits 30(3): 166-172 (1995)
Coauthor Index
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