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Nicholas C. Rumin
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2000 – 2009
- 2005
- [c10]Min Ma, Mourad Oulmane, Nicholas C. Rumin:
Explicit delay metric for interconnect optimization. ISCAS (3) 2005: 2453-2456 - 2001
- [j10]Mohamed Hafed, Mourad Oulmane, Nicholas C. Rumin:
Delay and current estimation in a CMOS inverter with an RC load. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(1): 80-89 (2001)
1990 – 1999
- 1999
- [c9]Anas A. Hamoui, Nicholas C. Rumin:
An analytical current, delay, and power model for the submicron CMOS inverter. ICECS 1999: 1547-1551 - 1996
- [c8]Jindrich Zejda, Eduard Cerny, S. Shenoy, Nicholas C. Rumin:
Bounding Switching Activity in CMOS Circuits Using Constraint Resolution. ED&TC 1996: 294-301 - 1994
- [j9]Abdolreza Nabavi-Lishi, Nicholas C. Rumin:
Inverter models of CMOS gates for supply current and delay evaluation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(10): 1271-1279 (1994) - [c7]Abdolreza Nabavi-Lishi, Nicholas C. Rumin:
Inverter-based Models for Current Analysis of CMOS Logic Circuits. ISCAS 1994: 13-16 - 1993
- [j8]Denis Martin, Nicholas C. Rumin:
Delay prediction from resistance-capacitance models of general MOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(7): 997-1003 (1993) - 1992
- [j7]Michel R. Dagenais, Serge Gaiotti, Nicholas C. Rumin:
Transistor-level estimation of worst-case delays in MOS VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(3): 384-395 (1992) - [j6]Eduard Cerny, John P. Hayes, Nicholas C. Rumin:
Accuracy of magnitude-class calculations in switch-level modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(4): 443-452 (1992) - [c6]Abdolreza Nabavi-Lishi, Nicholas C. Rumin:
Delay and bus current evaluation in CMOS logic circuits. ICCAD 1992: 198-203 - 1991
- [j5]Jean Paul Caisso, Eduard Cerny, Nicholas C. Rumin:
A recursive technique for computing delays in series-parallel MOS transistor circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(5): 589-595 (1991)
1980 – 1989
- 1989
- [j4]Michel R. Dagenais, Nicholas C. Rumin:
On the calculation of optimal clocking parameters in synchronous circuits with level-sensitive latches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(3): 268-278 (1989) - [c5]Serge Gaiotti, Michel R. Dagenais, Nicholas C. Rumin:
Worst-case Delay Estimation of Transistor Groups. DAC 1989: 491-495 - [c4]Eduard Cerny, John P. Hayes, Nicholas C. Rumin:
Magnitude classes in switch-level modeling. ICCD 1989: 284-288 - 1988
- [c3]Denis Martin, Nicholas C. Rumin:
Delay computation in switch-level models of non-treelike MOS circuits. ICCAD 1988: 358-361 - 1986
- [j3]Yvon Savaria, Jeremiah F. Hayes, Nicholas C. Rumin, Vinod K. Agarwal:
A Theory for the Design of Soft-Error-Tolerant VLSI Circuits. IEEE J. Sel. Areas Commun. 4(1): 15-23 (1986) - [j2]Yvon Savaria, Nicholas C. Rumin, Jeremiah F. Hayes, Vinold K. Agarwal:
Soft-error filtering: A solution to the reliability problem of future VLSI digital circuits. Proc. IEEE 74(5): 669-683 (1986) - [j1]Michel R. Dagenais, Vinod K. Agarwal, Nicholas C. Rumin:
McBOOLE: A New Procedure for Exact Logic Minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5(1): 229-238 (1986) - 1985
- [c2]Michel R. Dagenais, Vinod K. Agarwal, Nicholas C. Rumin:
The McBOOLE logic minimizer. DAC 1985: 667-673 - 1984
- [c1]Yvon Savaria, Vinod K. Agarwal, Nicholas C. Rumin, Jeremiah F. Hayes:
A Design for Machines with Built-In Tolerance to Soft Errors. ITC 1984: 649-659
Coauthor Index
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