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Jerome Quartana

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2000 – 2009

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2006
[c6]
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Pascal Manet, Jean-Baptiste Rigaud, Julien Francq, Marc Jeambrun, Assia Tria, Bruno Robisson, Jerome Quartana, Selma Laabidi:
Integrated Evaluation Platform for Secured Devices. ReCoSoC 2006: 214-219
2005
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Jerome Quartana, Salim Renane, Arnaud Baixas, Laurent Fesquet, Marc Renaudin:
GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips. FPL 2005: 299-304
[c4]
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Laurent Fesquet, Jerome Quartana, Marc Renaudin:
Asynchronous Systems on Programmable Logic. ReCoSoC 2005: 105-112
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Jerome Quartana, Laurent Fesquet, Marc Renaudin:
Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping. VLSI-SoC 2005: 195-207
2002
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Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Jerome Quartana:
High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems. DATE 2002: 1090
2001
[c1]
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Jean-Baptiste Rigaud, Jerome Quartana, Laurent Fesquet, Marc Renaudin:
Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems. VLSI-SOC 2001: 313-324

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