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2020 – today
- 2024
[j16]Sana Ibrahim
, Ali Al Shakoush, Serge Subias, Loic Vincent, Manuel J. Barragan Asian, Laurent Fesquet, Florence Podevin, Sylvain Bourdel:
Wideband Tunable N-Path Mixer With Calibrated Harmonic Rejection Including the 7th LO Harmonic. IEEE Trans. Circuits Syst. I Regul. Pap. 71(9): 3939-3950 (2024)- [c124]Xavier Lesage, Cristiano Merio, Fernando Welzel, Luca Sauer de Araujo, Sylvain Engels, Laurent Fesquet:
Data-driven Processing Element for Sparse Convolutional Neural Networks. NewCAS 2024: 143-147 - 2023
- [j15]Xavier Lesage, Rosalie Tran, Stéphane Mancini, Laurent Fesquet:
Velocity and Color Estimation Using Event-Based Clustering. Sensors 23(24): 9768 (2023) - [c123]Laurent Fesquet, Rosalie Tran, Xavier Lesage, Mohamed Akrarai, Stéphane Mancini, Gilles Sicard:
Low-Throughput Event-Based Image Sensors and Processing. DATE 2023: 1-6 - [c122]Hasan Moussa, Jessica Gonsalves, Estelle Lauga-Larroze, Sana Ibrahim, Florence Podevin, Sylvain Bourdel, Laurent Fesquet:
Making Digital N-Path Mixers. DCIS 2023: 1-5 - [c121]Diana Kalel, Jean-Christophe Brignone, Laurent Fesquet, Katell Morin-Allory:
A Generic CDC Modeling for Data Stability Verification. ICECS 2023: 1-4 - [c120]Cristiano Merio, Xavier Lesage, Ali Naimi, Sylvain Engels, Katell Morin-Allory, Laurent Fesquet:
Method for Data-Driven Pruning in Micropipeline Circuits. VLSI-SoC 2023: 1-6 - 2022
- [c119]Xavier Lesage, Rosalie Tran, Stéphane Mancini, Laurent Fesquet:
An improved event-by-event clustering algorithm for noisy acquisition. EBCCSP 2022: 1-8 - [c118]Alexis Rodrigo Iga Jadue, Sylvain Engels, Laurent Fesquet:
A Novel Event-Based Method for ASK Demodulation. LASCAS 2022: 1-4 - [c117]Ali Al Shakoush, Sana Ibrahim, Serge Subias, Florence Podevin, Manuel J. Barragán, Dayana A. Pino-Monroy, Imadeddine Bendjeddou, Estelle Lauga-Larroze, Laurent Fesquet, Thierry Taris, Sylvain Bourdel:
N-Path Mixer with Wide Rejection Including the 7th Harmonic for Low Power Multi-standard Receivers. NEWCAS 2022: 256-260 - [c116]Hasan Moussa, Sana Ibrahim, Estelle Lauga-Larroze, Florence Podevin, Sylvain Bourdel, Laurent Fesquet:
Self-Timed Ring Oscillators for Non-Overlapping and Overlapping Phases Synthesis. NEWCAS 2022: 357-360 - 2021
- [j14]Jérémy Belot, Abdelkarim Cherkaoui, Raphaël Laurent, Laurent Fesquet:
An Area- and Power-Efficient Stochastic Number Generator for Bayesian Sensor Fusion Circuits. IEEE Des. Test 38(6): 69-77 (2021) - [j13]Enagnon Aguénounon, Safa Razavinejad, Jean-Baptiste Schell, Mohammadreza Dolatpoor Lakeh, Wassim Khaddour, Foudil Dadouche, Jean-Baptiste Kammerer, Laurent Fesquet, Wilfried Uhring:
Design and Characterization of an Asynchronous Fixed Priority Tree Arbiter for SPAD Array Readout. Sensors 21(12): 3949 (2021) - [c115]Mohamed Akrarai, Nils Margotat, Gilles Sicard, Laurent Fesquet:
An asynchronous hybrid pixel image sensor. ASYNC 2021: 55-61 - [c114]Alexis Rodrigo Iga Jadue, Sylvain Engels, Laurent Fesquet:
Comparison between an ASK Event-Based Demodulation and a Digital IQ Demodulation. EBCCSP 2021: 1-4 - [c113]Assia El-Hadbi, Oussama Elissati, Laurent Fesquet:
Self-Timed Ring Oscillator based Time-to-Digital Converter: A 0.35μ m CMOS Proof-of-Concept Prototype. I2MTC 2021: 1-6 - [c112]Mohamed Akrarai, Nils Margotat, Gilles Sicard, Laurent Fesquet:
A hybrid event-based pixel for low-power image sensing. ICECS 2021: 1-6 - [c111]Jérémy Belot, Abdelkarim Cherkaoui, Raphaël Laurent, Laurent Fesquet:
An Energy Efficient Multi-Rail Architecture for Stochastic Computing: A Bayesian Sensor Fusion Case Study. ICECS 2021: 1-5 - [c110]Yoan Decoudu, Katell Morin-Allory, Laurent Fesquet:
A High-Level Design Flow for Locally Body Biased Asynchronous Circuits. VLSI-SoC 2021: 1-6 - 2020
- [j12]Ricardo Aquino Guazzelli, Matheus Garay Trindade, Leonel Acunha Guimaraes, Thiago Ferreira de Paiva Leite, Laurent Fesquet, Rodrigo Possamai Bastos:
Trojan Detection Test for Clockless Circuits. J. Electron. Test. 36(1): 23-31 (2020) - [c109]Grégoire Gimenez, Abdelkarim Cherkaoui, Laurent Fesquet:
A Self-Timed Ring based PUF. ASYNC 2020: 69-77 - [c108]Mohamed Akrarai, Nils Margotat, Gilles Sicard, Laurent Fesquet:
Arbiterless Event-Based Imager Architecture with temporal and spatial redundancies suppression. EBCCSP 2020: 1-6 - [c107]Saeed Mian Qaisar, Laurent Fesquet:
An Effective QRS Selection Based on the Level-Crossing Sampling and Activity Selection. EBCCSP 2020: 1-5 - [c106]Ricardo Aquino Guazzelli, Laurent Fesquet:
At-speed DfT Architecture for Bundled-data Design. ITC 2020: 1-9 - [c105]Ali Al Shakoush, Estelle Lauga-Larroze, Florence Podevin, Sana Ibrahim, Laurent Fesquet, Sylvain Bourdel:
Improved $\pi$-Delayed Harmonic Rejection N-Path Mixer for Low Power Consumption and Multistandard Receiver. NEWCAS 2020: 170-173 - [c104]Mohamed Akrarai, Nils Margotat, Gilles Sicard, Laurent Fesquet:
A Novel Event Based Image Sensor with spacial and temporal redundancy suppression. NEWCAS 2020: 238-241 - [c103]Yoan Decoudu, Jean Simatic, Katell Morin-Allory, Laurent Fesquet:
From High-Level Synthesis to Bundled-Data Circuits. SAMOS 2020: 200-212
2010 – 2019
- 2019
- [c102]Grégoire Gimenez, Jean Simatic, Laurent Fesquet:
From Signal Transition Graphs to Timing Closure: Application to Bundled-Data Circuits. ASYNC 2019: 86-95 - [c101]Ali Skaf, Mona Ezzadeen, Mounir Benabdenbi, Laurent Fesquet:
On-Line Adjustable Precision Computing. DTIS 2019: 1-5 - [c100]Brigitte Bidégaray-Fesquet, Laurent Fesquet:
A new synthesis approach for non-uniform filters in the log-scale: Proof of concept. EBCCSP 2019: 1-7 - [c99]Yoan Decoudu, Jean Simatic, Pauline Alexandre, Katell Morin-Allory, Laurent Fesquet:
Comparison of Synchronous and Asynchronous FIR Filter Architectures. EBCCSP 2019: 1-8 - [c98]Assia El-Hadbi, Oussama Elissati, Laurent Fesquet:
Time-to-Digital Converters: A Literature Review and New Perspectives. EBCCSP 2019: 1-8 - [c97]Alexis Rodrigo Iga Jadue, Sylvain Engels, Laurent Fesquet:
An Event-Based Strategy for ASK demodulation. EBCCSP 2019: 1-5 - [c96]Olivier Bonnaud, Laurent Fesquet, Ahmad Bsiesy:
Skilled manpower shortage in microelectronics: a challenge for the French education microelectronics network. ITHET 2019: 1-5 - [c95]Laurent Fesquet, Yoan Decoudu, Alexis Rodrigo Iga Jadue, Thiago Ferreira de Paiva Leite, Otto Aureliano Rolloff, M. Diallo, Rodrigo Possamai Bastos, Katell Morin-Allory, Sylvain Engels:
A Distributed Body-Biasing Strategy for Asynchronous Circuits. VLSI-SoC 2019: 27-32 - [c94]Alexis Rodrigo Iga Jadue, Sylvain Engels, Laurent Fesquet:
A Digital Event-Based Strategy for ASK demodulation. VLSI-SoC 2019: 244-245 - 2018
- [j11]Rodrigo Possamai Bastos, Leonel Acunha Guimaraes, Frank Sill Torres, Laurent Fesquet:
Architectures of bulk built-in current sensors for detection of transient faults in integrated circuits. Microelectron. J. 71: 70-79 (2018) - [j10]Thiago Ferreira de Paiva Leite, Laurent Fesquet, Rodrigo Possamai Bastos:
A body built-in cell for detecting transient faults and dynamically biasing subcircuits of integrated systems. Microelectron. Reliab. 88-90: 122-127 (2018) - [c93]Raphael Frisch, Marvin Faix, Emmanuel Mazer, Laurent Fesquet, Augustin Lux:
A Cognitive Stochastic Machine Based on Bayesian Inference: A Behavioral Analysis. ICCI*CC 2018: 124-131 - [c92]Sophie Germain, Sylvain Engels, Laurent Fesquet:
A Design Flow for Shaping Electromagnetic Emissions in Micropipeline Circuits. ASYNC 2018: 28-29 - [c91]Gregoire Gimenez, Abdelkarim Cherkaoui, Guillaume Cogniard, Laurent Fesquet:
Static Timing Analysis of Asynchronous Bundled-Data Circuits. ASYNC 2018: 110-118 - [c90]Mathieu Coustans, Abdelkarim Cherkaoui, Laurent Fesquet, Christian Terrier, Stephanie Salgado, Thomas Eberhardt, Maher Kayal:
Subthreshold logic for low-area and energy efficient true random number generator. COOL CHIPS 2018: 1-3 - [c89]Leonel Acunha Guimaraes, Thiago Ferreira de Paiva Leite, Rodrigo Possamai Bastos, Laurent Fesquet:
Non-intrusive testing technique for detection of Trojans in asynchronous circuits. DATE 2018: 1516-1519 - [c88]Oussama Elissati, Assia El-Hadbi, Abdelkarim Cherkaoui, Sébastien Rieubon, Laurent Fesquet:
Low Phase-Noise CMOS Quadrature Oscillator based on (N × 4)-stage Self-Timed Ring. DCIS 2018: 1-5 - [c87]Timothe Turko, Wilfried Uhring, Foudil Dadouche, Laurent Fesquet:
An Asynchronous Fixed Priority Arbiter for High througput Time Correlated Single Photon Counting Systems. ICECS 2018: 765-768 - [c86]Alexis Rodrigo Iga Jadue, Rodrigo Possamai Bastos, Thiago Ferreira de Paiva Leite, Otto Aureliano Rolloff, M. Diallo, Laurent Fesquet:
Level Shifter Architecture for Dynamically Biasing Ultra-Low Voltage Subcircuits of Integrated Systems. ISCAS 2018: 1-5 - [c85]Olivier Bonnaud, Laurent Fesquet, Luc Hébrard:
Strategy for higher education in electronic circuits and systems in the perspective of the up-coming digital society. LASCAS 2018: 1-4 - 2017
- [c84]Jean Simatic, Abdelkarim Cherkaoui, François Bertrand, Rodrigo Possamai Bastos, Laurent Fesquet:
A Practical Framework for Specification, Verification, and Design of Self-Timed Pipelines. ASYNC 2017: 65-72 - [c83]Amani Darwish, Hassan Abbass, Laurent Fesquet, Gilles Sicard:
Event-driven image sensor application: Event-driven image segmentation. EBCCSP 2017: 1-6 - [c82]Sophie Germain, Sylvain Engels, Laurent Fesquet:
Event-based design strategy for circuit electromagnetic compatibility. EBCCSP 2017: 1-7 - [c81]Saeed Mian Qaisar, Jean Simatic, Laurent Fesquet:
High-level synthesis of an event-driven windowing process. EBCCSP 2017: 1-8 - [c80]Arthur Kalsing, Laurent Fesquet, Chouki Aktouf:
Towards consistency checking between HDL and UPF descriptions. FDL 2017: 1-6 - [c79]Arthur Kalsing, Laurent Fesquet, Chouki Aktouf:
A Methodology for Automated Consistency Checking Between Different Power-Aware Descriptions. FDL (Selected Papers) 2017: 107-127 - [c78]François Bertrand, Abdelkarim Cherkaoui, Jean Simatic, Anthony Maure, Laurent Fesquet:
CAR: On the highway towards de-synchronization. ICECS 2017: 339-343 - [c77]Raphael Frisch, Raphaël Laurent, Marvin Faix, Laurent Girin, Laurent Fesquet, Augustin Lux, Jacques Droulez, Pierre Bessière, Emmanuel Mazer:
A Bayesian Stochastic Machine for Sound Source Localization. ICRC 2017: 1-8 - [c76]Ali Skaf, Jean Simatic, Laurent Fesquet:
Seeking low-power synchronous/asynchronous systems: A FIR implementation case study. ISCAS 2017: 1-4 - [c75]Leonel Acunha Guimaraes, Rodrigo Possamai Bastos, Laurent Fesquet:
Detection of Layout-Level Trojans by Monitoring Substrate with Preexisting Built-in Sensors. ISVLSI 2017: 290-295 - [c74]Gregoire Gimenez, Abdelkarim Cherkaoui, Raphael Frisch, Laurent Fesquet:
Self-timed Ring based True Random Number Generator: Threat model and countermeasures. IVSW 2017: 31-38 - [c73]Olivier Bonnaud, Laurent Fesquet:
Innovative practice in the French microelectronics education targeting the industrial needs. MSE 2017: 15-18 - [c72]Assia El-Hadbi, Abdelkarim Cherkaoui, Oussama Elissati, Jean Simatic, Laurent Fesquet:
On-the-fly and sub-gate-delay resolution TDC based on self-timed ring: A proof of concept. NEWCAS 2017: 305-308 - 2016
- [c71]Leonel Acunha Guimaraes, Rodrigo Possamai Bastos, Thiago Ferreira de Paiva Leite, Laurent Fesquet:
Simple tri-state logic Trojans able to upset properties of ring oscillators. DTIS 2016: 1-6 - [c70]Taha Beyrouthy, Ahmed Roshdy, Mohammad Salman, Saeed Mian Qaisar, Laurent Fesquet:
Asynchronous implementation of an event-driven adaptive FIR filter. EBCCSP 2016: 1-4 - [c69]Brigitte Bidégaray-Fesquet, Laurent Fesquet:
Levels, peaks, slopes... which sampling for which purpose? EBCCSP 2016: 1-6 - [c68]Jean Simatic, Rodrigo Possamai Bastos, Laurent Fesquet:
High-level synthesis for event-based systems. EBCCSP 2016: 1-7 - [c67]A. Ayres, Olivier Rozeau, B. Borot, Laurent Fesquet, Maud Vinet:
Delay partitioning helps reducing variability in 3DVLSI. ESSCIRC 2016: 75-78 - [c66]Olivier Bonnaud, Laurent Fesquet:
Practice in microelectronics education as a mandatory supplement to the future digital-based pedagogy: Strategy of the French national network. EWME 2016: 1-6 - [c65]Olivier Bonnaud, Laurent Fesquet:
MOOC and practices in electrical and information engineering: Complementary approaches. ITHET 2016: 1-4 - [c64]Thiago Ferreira de Paiva Leite, Rodrigo Possamai Bastos, Rodrigo Iga Jadue, Laurent Fesquet:
Comparison of low-voltage scaling in synchronous and asynchronous FD-SOI circuits. PATMOS 2016: 229-234 - [c63]Jean Simatic, Abdelkarim Cherkaoui, Rodrigo Possamai Bastos, Laurent Fesquet:
New asynchronous protocols for enhancing area and throughput in bundled-data pipelines. SBCCI 2016: 1-6 - 2015
- [j9]Otto Aureliano Rolloff, Rodrigo Possamai Bastos, Laurent Fesquet:
Exploiting reliable features of asynchronous circuits for designing low-voltage components in FD-SOI technology. Microelectron. Reliab. 55(9-10): 1302-1306 (2015) - [c62]Cansu Arslan, Julien Poujaud, Laurent Fesquet:
A method to automatically determine the level-crossing thresholds in non-uniform sampling and processing. EBCCSP 2015: 1-4 - [c61]Taha Beyrouthy, Laurent Fesquet, Robin Rolland:
Data sampling and processing: Uniform vs. non-uniform schemes. EBCCSP 2015: 1-6 - [c60]Amani Darwish, Laurent Fesquet, Gilles Sicard:
RTL simulation of an asynchronous reading architecture for an event-driven image sensor. EBCCSP 2015: 1-4 - [c59]Olivier Bonnaud, Laurent Fesquet:
Communicating and smart objects: Multidisciplinary topics for the innovative education in microelectronics and its applications. ITHET 2015: 1-5 - [c58]Olivier Bonnaud, Laurent Fesquet:
Towards multidisciplinarity for microelectronics education: A strategy of the French national network. MSE 2015: 1-4 - [c57]Chadi Al Khatib, Claire Aupetit, Cyril Chevalier, Chouki Aktouf, Gilles Sicard, Laurent Fesquet:
A generic clock controller for low power systems: Experimentation on an AXI bus. VLSI-SoC 2015: 307-312 - 2014
- [j8]Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin:
Adaptive rate filtering a computationally efficient signal processing approach. Signal Process. 94: 620-630 (2014) - [c56]Amani Darwish, Gilles Sicard, Laurent Fesquet:
Low data rate architecture for smart image sensor. IMSE 2014: 902206 - [c55]Olivier Bonnaud, Laurent Fesquet:
Trends in nanoelectronic education from FDSOI and FinFET technologies to circuit design specifications. EWME 2014: 106-111 - [c54]Chadi Al Khatib, Claire Aupetit, Alejandro Chagoya, Cyril Chevalier, Gilles Sicard, Laurent Fesquet:
Distributed asynchronous controllers for clock management in low power systems. ICECS 2014: 379-382 - [c53]Olivier Bonnaud, Pascal Nouet, Laurent Fesquet, Taieb Mohammed-Brahim:
FINMINA: A French national project to promote innovation in higher education in microelectronics and nanotechnologies. ITHET 2014: 1-8 - [c52]Amani Darwish, Laurent Fesquet, Gilles Sicard:
1-Level crossing sampling scheme for low data rate image sensors. NEWCAS 2014: 289-292 - [c51]Laurent Fesquet, Abdelkarim Cherkaoui, Oussama Elissati:
Self-timed rings as low-phase noise programmable oscillators. NEWCAS 2014: 409-412 - [c50]Giuseppe Roa, Tugdual Le Pelleter, Agnès Bonvilain, Alejandro Chagoya, Laurent Fesquet:
Designing ultra-low power systems with non-uniform sampling and event-driven logic. SBCCI 2014: 5:1-5:6 - 2013
- [j7]Taha Beyrouthy, Laurent Fesquet:
An Asynchronous FPGA Block with Its Tech-Mapping Algorithm Dedicated to Security Applications. Int. J. Reconfigurable Comput. 2013: 517947:1-517947:12 (2013) - [c49]Przemyslaw Sliwinski, Krzysztof S. Berezowski, Pawel Wachel, Gilles Sicard, Laurent Fesquet:
Empirical Recovery of Input Nonlinearity in Distributed Element Models. ALCOSP 2013: 617-622 - [c48]Eslam Yahya, Laurent Fesquet, Yehea I. Ismail, Marc Renaudin:
Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using Model-Based Simulation. ASYNC 2013: 67-74 - [c47]Abdelkarim Cherkaoui, Viktor Fischer, Alain Aubert, Laurent Fesquet:
A Self-Timed Ring Based True Random Number Generator. ASYNC 2013: 99-106 - [c46]Abdelkarim Cherkaoui, Viktor Fischer, Laurent Fesquet, Alain Aubert:
A Very High Speed True Random Number Generator with Entropy Assessment. CHES 2013: 179-196 - [c45]Olivier Bonnaud, Laurent Fesquet:
Innovating projects as a pedagogical strategy for the French network for education in microélectronics and nanotechnologies. MSE 2013: 5-8 - 2012
- [c44]Abdelkarim Cherkaoui, Viktor Fischer, Alain Aubert, Laurent Fesquet:
Comparison of Self-Timed Ring and Inverter Ring Oscillators as entropy sources in FPGAs. DATE 2012: 1325-1330 - [c43]Evelyne Excoffon, Francine Papillon, Laurent Fesquet, Ahmad Bsiesy, Olivier Bonnaud:
New pedagogical experiment leading to awareness in nanosciences and nanotechnologies for young generations at secondary school. ITHET 2012: 1-4 - 2011
- [j6]Hatem Zakaria, Laurent Fesquet:
Designing a Process Variability Robust Energy-Efficient Control for Complex SoCs. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(2): 160-172 (2011) - [c42]Chao Yan, Florent Ouchet, Laurent Fesquet, Katell Morin-Allory:
Formal Verification of C-element Circuits. ASYNC 2011: 55-64 - [c41]Alexandre Porcher, Katell Morin-Allory, Laurent Fesquet, Alejandro Chagoya:
Does asynchronous technology bring robustness in synchronous circuit monitoring? FDL 2011: 1-6 - [c40]Florent Ouchet, Katell Morin-Allory, Laurent Fesquet:
C-elements for Hardened Self-timed Circuits. PATMOS 2011: 247-256 - [c39]Taha Beyrouthy, Laurent Fesquet:
An event-driven FIR filter: Design and implementation. International Symposium on Rapid System Prototyping 2011: 59-65 - [i3]Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin:
A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback. CoRR abs/1103.1360 (2011) - 2010
- [j5]Laurent Fesquet, Brigitte Bidégaray-Fesquet:
IIR digital filtering of non-uniformly sampled signals via state representation. Signal Process. 90(10): 2811-2821 (2010) - [c38]Florent Ouchet, Katell Morin-Allory, Laurent Fesquet:
Delay Insensitivity Does Not Mean Slope Insensitivity! ASYNC 2010: 176-184 - [c37]Alexandre Porcher, Katell Morin-Allory, Laurent Fesquet:
Synthesis of asynchronous monitors for critical electronic systems. DDECS 2010: 329-334 - [c36]Laurent Fesquet, Gilles Sicard, Brigitte Bidégaray-Fesquet:
Targeting ultra-low power consumption with non-uniform sampling and filtering. ISCAS 2010: 3585-3588 - [c35]Oussama Elissati, Eslam Yahya, Sébastien Rieubon, Laurent Fesquet:
Optimizing and Comparing CMOS Implementations of the C-Element in 65nm Technology: Self-Timed Ring Case. PATMOS 2010: 137-149 - [c34]Oussama Elissati, Sébastien Rieubon, Eslam Yahya, Laurent Fesquet:
Self-Timed Rings: A Promising Solution for Generating High-Speed High-Resolution Low-Phase Noise Clocks. VLSI-SoC (Selected Papers) 2010: 22-42 - [c33]Oussama Elissati, Eslam Yahya, Sébastien Rieubon, Laurent Fesquet:
A high-speed high-resolution low-phase noise oscillator using self-timed rings. VLSI-SoC 2010: 173-178
2000 – 2009
- 2009
- [j4]Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin:
Adaptive Rate Sampling and Filtering Based on Level Crossing Sampling. EURASIP J. Adv. Signal Process. 2009 (2009) - [j3]Jérémie Hamon, Laurent Fesquet, Benoit Miscopein, Marc Renaudin:
Constrained Asynchronous Ring Structures for Robust Digital Oscillators. IEEE Trans. Very Large Scale Integr. Syst. 17(7): 907-919 (2009) - [c32]Laurent Fesquet, Hatem Zakaria:
Controlling energy and process variability in System-on-Chips: needs for control theory. CCA/ISIC 2009: 302-307 - [c31]Eslam Yahya, Oussama Elissati, Hatem Zakaria, Laurent Fesquet, Marc Renaudin:
Programmable/Stoppable Oscillator Based on Self-Timed Rings. ASYNC 2009: 3-12 - [c30]Khaled Alsayeg, Katell Morin-Allory, Laurent Fesquet:
RAT-based formal verification of QDI asynchronous controllers. FDL 2009: 1-6 - [c29]Eslam Yahya, Laurent Fesquet:
Asynchronous design: A promising paradigm for electronic circuits and systems. ICECS 2009: 339-342 - [c28]Sylvain Guilley, Sumanta Chaudhuri, Laurent Sauvage, Jean-Luc Danger, Taha Beyrouthy, Laurent Fesquet:
Updates on the potential of clock-less logics to strengthen cryptographic circuits against side-channel attacks. ICECS 2009: 351-354 - 2008
- [j2]Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin:
An Adaptive Resolution Computationally Efficient Short-Time Fourier Transform. J. Electr. Comput. Eng. 2008 (2008) - [c27]Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin:
Physical Design of FPGA Interconnect to Prevent Information Leakage. ARC 2008: 87-98 - [c26]Jérémie Hamon, Laurent Fesquet, Benoit Miscopein, Marc Renaudin:
High-Level Time-Accurate Model for the Design of Self-Timed Ring Oscillators. ASYNC 2008: 29-38 - [i2]Philippe Hoogvorst, Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Taha Beyrouthy, Laurent Fesquet:
A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks. CoRR abs/0809.3942 (2008) - 2007
- [c25]Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin:
Computationally efficient adaptive rate sampling and filtering. EUSIPCO 2007: 2139-2143 - [c24]Katell Morin-Allory, Laurent Fesquet, Benjamin Roustan, Dominique Borrione:
Asynchronous online-monitoring of logical and temporal assertions. FDL 2007: 286-290 - [c23]Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin, Sumanta Chaudhuri, Sylvain Guilley, Jean-Luc Danger, Philippe Hoogvorst:
A Novel Asynchronous e-FPGA Architecture for Security Applications. FPT 2007: 369-372 - [c22]Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin:
Adaptive Rate Filtering Fora Signal Driven Sampling Scheme. ICASSP (3) 2007: 1465-1468 - [c21]Philippe Hoogvorst, Sylvain Guilley, Sumanta Chaudhuri, Alin Razafindraibe, Taha Beyrouthy, Laurent Fesquet:
A Reconfigurable Cell for a Multi-Style Asynchronous FPGA. ReCoSoC 2007: 15-22 - [i1]N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin:
FPGA Architecture for Multi-Style Asynchronous Logic. CoRR abs/0710.4711 (2007) - 2006
- [c20]Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin:
Spectral analysis of a signal driven sampling scheme. EUSIPCO 2006: 1-5 - [c19]Katell Morin-Allory, Laurent Fesquet, Dominique Borrione:
Asynchronous Assertion Monitors for multi-Clock Domain System Verification. IEEE International Workshop on Rapid System Prototyping 2006: 98-102 - [c18]Laurent Fesquet, Bertrand Folco, Mathieu Steiner, Marc Renaudin:
State-holding in Look-Up Tables: application to asynchronous logic. VLSI-SoC 2006: 12-17 - 2005
- [c17]N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin:
FPGA Architecture for Multi-Style Asynchronous Logic. DATE 2005: 32-33 - [c16]D. Borionne, M. Liu, P. Ostier, Laurent Fesquet:
PSL-based online monitoring of digital systems. FDL 2005: 465-479 - [c15]Laurent Fesquet, Marc Renaudin:
A Programmable Logic Architecture for Prototyping Clockless Circuits. FPL 2005: 293-298 - [c14]Jerome Quartana, Salim Renane, Arnaud Baixas, Laurent Fesquet, Marc Renaudin:
GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips. FPL 2005: 299-304 - [c13]Laurent Fesquet, Jerome Quartana, Marc Renaudin:
Asynchronous Systems on Programmable Logic. ReCoSoC 2005: 105-112 - [c12]Bertrand Folco, Vivian Brégier, Laurent Fesquet, Marc Renaudin:
Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits. VLSI-SoC 2005: 55-69 - [c11]Jerome Quartana, Laurent Fesquet, Marc Renaudin:
Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping. VLSI-SoC 2005: 195-207 - [e1]Laurent Fesquet, Andreas Kaiser, Sorin Cristoloveanu, Michel Brillouët:
Proceedings of the 31st European Solid-State Circuits Conference, ESSCIRC 2005, Grenoble, France, 12-16 September 2005. IEEE 2005, ISBN 0-7803-9205-1 [contents] - 2004
- [j1]Laurent Fesquet, Mohammed Es Salhiene, Marc Renaudin:
La technologie asynchrone au service de la réduction d'énergie dans les systèmes embarqués. Ann. des Télécommunications 59(7-8): 984-997 (2004) - [c10]F. Aeschlimann, Emmanuel Allier, Laurent Fesquet, Marc Renaudin:
Asynchronous FIR Filters: Towards a New Digital Processing Chain. ASYNC 2004: 198-206 - 2003
- [c9]Emmanuel Allier, Gilles Sicard, Laurent Fesquet, Marc Renaudin:
A New Class of Asynchronous A/D Converters Based on Time Quantization. ASYNC 2003: 196-205 - 2002
- [c8]Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Jerome Quartana:
High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems. DATE 2002: 1090 - [c7]Quoc Thai Ho, Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Robin Rolland:
Implementing Asynchronous Circuits on LUT Based FPGAs. FPL 2002: 36-46 - [c6]Anh Vu Dihn Duc, Laurent Fesquet, Marc Renaudin:
Synthesis of QDI Asynchronous Circuits from DTL-Style Petri-Net. IWLS 2002: 191-196 - [c5]Emmanuel Allier, Laurent Fesquet, Marc Renaudin, Gilles Sicard:
Low-Power Asynchronous A/D Conversion. PATMOS 2002: 81-91 - [c4]Mohammed Es Salhiene, Laurent Fesquet, Marc Renaudin:
Dynamic Voltage Scheduling for Real Time Asynchronous Systems. PATMOS 2002: 390-399 - 2001
- [c3]Jean-Baptiste Rigaud, Jerome Quartana, Laurent Fesquet, Marc Renaudin:
Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems. VLSI-SOC 2001: 313-324
1990 – 1999
- 1999
- [c2]Wissam Hlayhel, Jacques Henri Collet, Laurent Fesquet:
Implementing Snoop-Coherence Protocol for Future SMP Architectures. Euro-Par 1999: 745-752 - 1998
- [c1]Wissam Hlayhel, Daniel Litaize, Laurent Fesquet, Jacques Henri Collet:
Optical versus Electronic Bus for Address-Transactions in Future SMP Architectures. IEEE PACT 1998: 22-29
Coauthor Index
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