default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDTakayasu Sakurai
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
[j96]Thatree Mamee
, Zaiqi Lou, Katsuhiro Hata, Makoto Takamiya, Takayasu Sakurai, Shinichi Nishizawa, Wataru Saito:
Estimating of IGBT Bond Wire Lift-Off Trend Using Convolutional Neural Network (CNN). IEEE Access 12: 96936-96945 (2024)- 2022
- [j95]Hao Qiu, Takayasu Sakurai, Makoto Takamiya:
A 6.78-MHz Multiple-Transmitter Wireless Power Transfer System With Efficiency Maximization by Adaptive Magnetic Field Adder IC. IEEE J. Solid State Circuits 57(8): 2390-2403 (2022) - [j94]Yu-Shan Cheng, Daiki Yamaguchi, Tomoyuki Mannen, Keiji Wada, Toru Sai, Koutaro Miyazaki, Makoto Takamiya, Takayasu Sakurai:
High-Speed Searching of Optimum Switching Pattern for Digital Active Gate Drive to Adapt to Various Load Conditions. IEEE Trans. Ind. Electron. 69(5): 5185-5194 (2022) - 2021
- [j93]Hao Qiu, Yuntao Jiang, Yi Shi, Takayasu Sakurai, Makoto Takamiya:
Analysis and Mitigation of Coupling-Dependent Data Flipping in Wireless Power and Data Transfer System. IEEE Trans. Circuits Syst. I Regul. Pap. 68(12): 5182-5193 (2021)
2010 – 2019
- 2019
- [j92]Teruki Someya, A. K. M. Mahfuzul Islam, Takayasu Sakurai, Makoto Takamiya:
An 11-nW CMOS Temperature-to-Digital Converter Utilizing Sub-Threshold Current at Sub-Thermal Drain Voltage. IEEE J. Solid State Circuits 54(3): 613-622 (2019) - [j91]Teruki Someya, Kenichi Matsunaga, Hiroki Morimura, Takayasu Sakurai, Makoto Takamiya:
A 0.90-4.39-V Detection Voltage Range, 56-Level Programmable Voltage Detector Using Fine Voltage-Step Subtraction for Battery Management. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(3): 1270-1279 (2019) - [c123]Tsukasa Kagaya, Koutaro Miyazaki, Makoto Takamiya, Takayasu Sakurai:
A 500-Mbps Digital Isolator Circuits using Counter-Pulse Immune Receiver Scheme for Power Electronics. ICICDT 2019: 1-4 - [c122]Koutaro Miyazaki, Yang Lo, A. K. M. Mahfuzul Islam, Katsuhiro Hata, Makoto Takamiya, Takayasu Sakurai:
CNN-based Approach for Estimating Degradation of Power Devices by Gate Waveform Monitoring. ICICDT 2019: 1-4 - [c121]Yu-Shan Cheng, Daiki Yamaguchi, Tomoyuki Mannen, Keiji Wada, Toru Sai, Koutaro Miyazaki, Makoto Takamiya, Takayasu Sakurai:
Digital Active Gate Drive with Optimal Switching Patterns to Adapt to Sinusoidal Output Current in a Full Bridge Inverter Circuit. IECON 2019: 1684-1689 - [c120]Hao Qiu, Takayasu Sakurai, Makoto Takamiya:
Coupling-Dependent Data Flipping in Wireless Power and Data Transfer System. ISCAS 2019: 1-5 - 2018
- [j90]Toru Sai, Yoshitaka Yamauchi, Hajime Kando, Tatsuya Funaki, Takayasu Sakurai, Makoto Takamiya:
2/3 and 1/2 Reconfigurable Switched Capacitor DC-DC Converter With 92.9% Efficiency at 62 mW/mm2 Using Driver Amplitude Doubler. IEEE Trans. Circuits Syst. II Express Briefs 65-II(11): 1654-1658 (2018) - [j89]Chung-Shiang Wu, Makoto Takamiya, Takayasu Sakurai:
Clocked Hysteresis Control Scheme With Power-Law Frequency Scaling in Buck Converter to Improve Light-Load Efficiency for IoT Sensor Nodes. IEEE Trans. Very Large Scale Integr. Syst. 26(6): 1139-1150 (2018) - [c119]Teruki Someya, Islam A. K. M. Mahfuzul, Takayasu Sakurai, Makoto Takamiya:
A 13nW temperature-to-digital converter utilizing sub-threshold MOSFET operation at sub-thermal drain voltage. CICC 2018: 1-4 - 2017
- [j88]Islam A. K. M. Mahfuzul, Masamune Hamamatsu, Tomoyuki Yokota, Sunghoon Lee, Wakako Yukita, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
Programmable Neuron Array Based on a 2-Transistor Multiplier Using Organic Floating-Gate for Intelligent Sensors. IEEE J. Emerg. Sel. Topics Circuits Syst. 7(1): 81-91 (2017) - [j87]Teruki Someya, Hiroshi Fuketa, Kenichi Matsunaga, Hiroki Morimura, Takayasu Sakurai, Makoto Takamiya:
Design and Analysis of Ultra-Low Power Glitch-Free Programmable Voltage Detector Based on Multiple Voltage Copier. IEICE Trans. Electron. 100-C(4): 349-358 (2017) - [j86]Shunta Iguchi, Takayasu Sakurai, Makoto Takamiya:
A Low-Power CMOS Crystal Oscillator Using a Stacked-Amplifier Architecture. IEEE J. Solid State Circuits 52(11): 3006-3017 (2017) - [c118]Chung-Shiang Wu, Makoto Takamiya, Takayasu Sakurai:
Buck converter with higher than 87% efficiency over 500nA to 20mA load current range for IoT sensor nodes by Clocked Hysteresis Control. CICC 2017: 1-4 - [c117]Yoshitaka Yamauchi, Toru Sai, Takayasu Sakurai, Makoto Takamiya:
Modeling of 3-level buck converters in discontinuous conduction mode for stand-by mode power supply. ISCAS 2017: 1-4 - 2016
- [j85]Shunta Iguchi, Hiroshi Fuketa, Takayasu Sakurai, Makoto Takamiya:
Variation-Tolerant Quick-Start-Up CMOS Crystal Oscillator With Chirp Injection and Negative Resistance Booster. IEEE J. Solid State Circuits 51(2): 496-508 (2016) - [c116]Teruki Someya, Kenichi Matsunaga, Hiroki Morimura, Takayasu Sakurai, Makoto Takamiya:
56-Level programmable voltage detector in steps of 50mV for battery management. A-SSCC 2016: 49-52 - [c115]Shunta Iguchi, Takayasu Sakurai, Makoto Takamiya:
5.7 A 39.25MHz 278dB-FOM 19µW LDO-free stacked-amplifier crystal oscillator (SAXO) operating at I/O voltage. ISSCC 2016: 100-101 - 2015
- [j84]Shunta Iguchi, Pyungwoo Yeon, Hiroshi Fuketa, Koichi Ishida, Takayasu Sakurai, Makoto Takamiya:
Wireless Power Transfer With Zero-Phase-Difference Capacitance Control. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(4): 938-947 (2015) - [c114]Dan Luo, Hiroshi Fuketa, Kenichi Matsunaga, Hiroki Morimura, Makoto Takamiya, Takayasu Sakurai:
Analysis to optimize sensitivity of RF energy harvester with voltage boost circuit. ECCTD 2015: 1-4 - [c113]Teruki Someya, Hiroshi Fuketa, Kenichi Matsunaga, Hiroki Morimura, Takayasu Sakurai, Makoto Takamiya:
248pW, 0.11mV/°C glitch-free programmable voltage detector with multiple voltage duplicator for energy harvesting. ESSCIRC 2015: 249-252 - [c112]Yoshitaka Yamauchi, Yuki Yanagihara, Hiroshi Fuketa, Takayasu Sakurai, Makoto Takamiya:
Optimal design to maximize efficiency of single-inductor multiple-output buck converters in discontinuous conduction mode for IoT applications. ICICDT 2015: 1-4 - [c111]Hiroshi Fuketa, Masamune Hamamatsu, Tomoyuki Yokota, Wakako Yukita, Teruki Someya, Tsuyoshi Sekitani, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
16.4 Energy-autonomous fever alarm armband integrating fully flexible solar cells, piezoelectric speaker, temperature detector, and 12V organic complementary FET circuits. ISSCC 2015: 1-3 - 2014
- [j83]Hiroshi Fuketa, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai:
Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits. IEEE J. Solid State Circuits 49(2): 536-544 (2014) - [j82]Xin Zhang, Po-Hung Chen, Yasuyuki Okuma, Koichi Ishida, Yoshikatsu Ryu, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya:
A 0.6 V Input CCM/DCM Operating Digital Buck Converter in 40 nm CMOS. IEEE J. Solid State Circuits 49(11): 2377-2386 (2014) - [j81]Hiroshi Fuketa, Kazuaki Yoshioka, Yasuhiro Shinozuka, Koichi Ishida, Tomoyuki Yokota, Naoji Matsuhisa, Yusuke Inoue, Masaki Sekino, Tsuyoshi Sekitani, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
1 µm-Thickness Ultra-Flexible and High Electrode-Density Surface Electromyogram Measurement Sheet With 2 V Organic Transistors for Prosthetic Hand Control. IEEE Trans. Biomed. Circuits Syst. 8(6): 824-833 (2014) - [j80]Shunta Iguchi, Akira Saito, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya:
Design Method of Class-F Power Amplifier With Output Power of -20 dBm and Efficient Dual Supply Voltage Transmitter. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(10): 2978-2986 (2014) - [c110]Hiroshi Fuketa, Youichi Momiyama, Atsushi Okamoto, Tsuyoshi Sakata, Makoto Takamiya, Takayasu Sakurai:
An 85-mV input, 50-µs startup fully integrated voltage multiplier with passive clock boost using on-chip transformers for energy harvesting. ESSCIRC 2014: 263-266 - [c109]Hiroshi Fuketa, Kazuaki Yoshioka, Tomoyuki Yokota, Wakako Yukita, Mari Koizumi, Masaki Sekino, Tsuyoshi Sekitani, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
30.3 Organic-transistor-based 2kV ESD-tolerant flexible wet sensor sheet for biomedical applications with wireless power and data transmission using 13.56MHz magnetic resonance. ISSCC 2014: 490-491 - [c108]Makoto Takamiya, Hiroshi Fuketa, Koichi Ishida, Tomoyuki Yokota, Tsuyoshi Sekitani, Takao Someya, Takayasu Sakurai:
Flexible, large-area, and distributed organic electronics closely contacted with skin for healthcare applications. MWSCAS 2014: 829-832 - [c107]Shunta Iguchi, Hiroshi Fuketa, Takayasu Sakurai, Makoto Takamiya:
92% start-up time reduction by variation-tolerant chirp injection (CI) and negative resistance booster (NRB) in 39MHz crystal oscillator. VLSIC 2014: 1-2 - 2013
- [j79]Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Yasuhiro Shinozuka, Hiroshi Fuketa, Tomoyuki Yokota, Ute Zschieschang, Hagen Klauk, Gregory Tortissier, Tsuyoshi Sekitani, Hiroshi Toshiyoshi, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
Insole Pedometer With Piezoelectric Energy Harvester and 2 V Organic Circuits. IEEE J. Solid State Circuits 48(1): 255-264 (2013) - [j78]Shinji Miyano, Shinichi Moriwaki, Yasue Yamamoto, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Hirofumi Shinohara:
Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges. IEEE J. Solid State Circuits 48(4): 924-931 (2013) - [j77]Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic Circuits. IEEE J. Solid State Circuits 48(8): 1986-1994 (2013) - [j76]Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: VDDmin-Aware Dual Supply Voltage Technique. IEEE Trans. Very Large Scale Integr. Syst. 21(6): 1175-1179 (2013) - [c106]Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
Variation-aware subthreshold logic circuit design. ASICON 2013: 1-4 - [c105]Shunta Iguchi, Akira Saito, Kentaro Honda, Yun Fei Zheng, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya:
315MHz OOK transceiver with 38-µW receiver and 36-µW transmitter in 40-nm CMOS. ASP-DAC 2013: 93-94 - [c104]Xin Zhang, Po-Hung Chen, Yoshikatsu Ryu, Koichi Ishida, Yasuyuki Okuma, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya:
A low voltage buck DC-DC converter using on-chip gate boost technique in 40nm CMOS. ASP-DAC 2013: 109-110 - [c103]Tsuyoshi Sekitani, Tomoyuki Yokota, Makoto Takamiya, Takayasu Sakurai, Takao Someya:
Electrical artificial skin using ultraflexible organic transistor. DAC 2013: 125:1-125:3 - [c102]Yasuhiro Shinozuka, Hiroshi Fuketa, Koichi Ishida, Futoshi Furuta, Kenichi Osada, Kenichi Takeda, Makoto Takamiya, Takayasu Sakurai:
Reducing IR drop in 3D integration to less than 1/4 using Buck Converter on Top die (BCT) scheme. ISQED 2013: 210-215 - [c101]Hiroshi Fuketa, Kazuaki Yoshioka, Yasuhiro Shinozuka, Koichi Ishida, Tomoyuki Yokota, Naoji Matsuhisa, Yusuke Inoue, Masaki Sekino, Tsuyoshi Sekitani, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
1µm-thickness 64-channel surface electromyogram measurement sheet with 2V organic transistors for prosthetic hand control. ISSCC 2013: 104-105 - [c100]Hiroshi Fuketa, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai:
Intermittent resonant clocking enabling power reduction at any clock frequency for 0.37V 980kHz near-threshold logic circuits. ISSCC 2013: 436-437 - [c99]Hiroshi Fuketa, Koichi Ishida, Tsuyoshi Sekitani, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
Large-area and flexible sensors with organic transistors. IWASI 2013: 87-90 - 2012
- [j75]Lechang Liu, Takayasu Sakurai, Makoto Takamiya:
A 315 MHz Power-Gated Ultra Low Power Transceiver in 40 nm CMOS for Wireless Sensor Network. IEICE Trans. Electron. 95-C(6): 1035-1041 (2012) - [j74]Naoki Masunaga, Koichi Ishida, Takayasu Sakurai, Makoto Takamiya:
EMI Camera LSI (EMcam) with On-Chip Loop Antenna Matrix to Measure EMI Noise Spectrum and Distribution. IEICE Trans. Electron. 95-C(6): 1059-1066 (2012) - [j73]Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Tsuyoshi Sekitani, Hiroyoshi Nakajima, Hiroki Maeda, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
A 100-V AC Energy Meter Integrating 20-V Organic CMOS Digital and Analog Circuits With a Floating Gate for Process Variation Compensation and a 100-V Organic pMOS Rectifier. IEEE J. Solid State Circuits 47(1): 301-309 (2012) - [j72]Po-Hung Chen, Koichi Ishida, Katsuyuki Ikeuchi, Xin Zhang, Kentaro Honda, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai:
Startup Techniques for 95 mV Step-Up Converter by Capacitor Pass-On Scheme and VTH-Tuned Oscillator With Fixed Charge Programming. IEEE J. Solid State Circuits 47(5): 1252-1260 (2012) - [j71]Po-Hung Chen, Xin Zhang, Koichi Ishida, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai:
An 80 mV Startup Dual-Mode Boost Converter by Charge-Pumped Pulse Generator and Threshold Voltage Tuned Oscillator With Hot Carrier Injection. IEEE J. Solid State Circuits 47(11): 2554-2562 (2012) - [j70]Xin Zhang, Yu Pu, Koichi Ishida, Yoshikatsu Ryu, Yasuyuki Okuma, Po-Hung Chen, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya:
A 1-V-Input Switched-Capacitor Voltage Converter With Voltage-Reference-Free Pulse-Density Modulation. IEEE Trans. Circuits Syst. II Express Briefs 59-II(6): 361-365 (2012) - [j69]Ryo Takahashi, Hidehiro Takata, Tadashi Yasufuku, Hiroshi Fuketa, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature. IEEE Trans. Circuits Syst. II Express Briefs 59-II(12): 918-921 (2012) - [j68]Xin Zhang, Koichi Ishida, Hiroshi Fuketa, Makoto Takamiya, Takayasu Sakurai:
On-Chip Measurement System for Within-Die Delay Variation of Individual Standard Cells in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 20(10): 1876-1880 (2012) - [c98]Po-Hung Chen, Koichi Ishida, Xin Zhang, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai:
A 120-mV input, fully integrated dual-mode charge pump in 65-nm CMOS for thermoelectric energy harvester. ASP-DAC 2012: 469-470 - [c97]Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits. CICC 2012: 1-4 - [c96]Shunta Iguchi, Akira Saito, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya:
2.1 Times increase of drain efficiency by dual supply voltage scheme in 315MHz class-F Power amplifier at output power of -20dBm. ESSCIRC 2012: 345-348 - [c95]Akira Saito, Yun Fei Zheng, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya:
0.35V, 4.1μW, 39MHz crystal oscillator in 40nm CMOS. ISLPED 2012: 333-338 - [c94]Tadashi Yasufuku, Koji Hirairi, Yu Pu, Yun Fei Zheng, Ryo Takahashi, Masato Sasaki, Hiroshi Fuketa, Atsushi Muramatsu, Masahiro Nomura, Hirofumi Shinohara, Makoto Takamiya, Takayasu Sakurai:
24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits. ISQED 2012: 586-591 - [c93]Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Yasuhiro Shinozuka, Hiroshi Fuketa, Tomoyuki Yokota, Ute Zschieschang, Hagen Klauk, Gregory Tortissier, Tsuyoshi Sekitani, Makoto Takamiya, Hiroshi Toshiyoshi, Takao Someya, Takayasu Sakurai:
Insole pedometer with piezoelectric energy harvester and 2V organic digital and analog circuits. ISSCC 2012: 308-310 - [c92]Koji Hirairi, Yasuyuki Okuma, Hiroshi Fuketa, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO. ISSCC 2012: 486-488 - [c91]Takayasu Sakurai:
Ambient electronics and ultra-low power LSI design. VLSI-DAT 2012: 1-31 - [c90]Akira Saito, Kentaro Honda, Yun Fei Zheng, Shunta Iguchi, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya:
An all 0.5V, 1Mbps, 315MHz OOK transceiver with 38-µW career-frequency-free intermittent sampling receiver and 52-µW class-F transmitter in 40-nm CMOS. VLSIC 2012: 38-39 - [c89]Shinichi Moriwaki, Yasuhiro Yamamoto, Atsushi Kawasumi, Toshikazu Suzuki, Shinji Miyano, Takayasu Sakurai, Hirofumi Shinohara:
A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges. VLSIC 2012: 60-61 - [c88]Xin Zhang, Po-Hung Chen, Yoshikatsu Ryu, Koichi Ishida, Yasuyuki Okuma, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya:
A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2µW to 50µW. VLSIC 2012: 194-195 - 2011
- [j67]Po-Hung Chen, Koichi Ishida, Xin Zhang, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai:
0.18-V Input Charge Pump with Forward Body Bias to Startup Boost Converter for Energy Harvesting Applications. IEICE Trans. Electron. 94-C(4): 598-604 (2011) - [j66]Yasuyuki Okuma, Koichi Ishida, Yoshikatsu Ryu, Xin Zhang, Po-Hung Chen, Kazunori Watanabe, Makoto Takamiya, Takayasu Sakurai:
0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7% Current Efficiency in 65 nm CMOS. IEICE Trans. Electron. 94-C(6): 938-944 (2011) - [j65]Xin Zhang, Yu Pu, Koichi Ishida, Yoshikatsu Ryu, Yasuyuki Okuma, Po-Hung Chen, Takayasu Sakurai, Makoto Takamiya:
A Variable Output Voltage Switched-Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57% Ripple Reduction at Low Output Voltage. IEICE Trans. Electron. 94-C(6): 953-959 (2011) - [j64]Lechang Liu, Takayasu Sakurai, Makoto Takamiya:
0.6 V Voltage Shifter and Clocked Comparator for Sampling Correlation-Based Impulse Radio UWB Receiver. IEICE Trans. Electron. 94-C(6): 985-991 (2011) - [j63]Katsuyuki Ikeuchi, Hideki Kusamitsu, Mutsuo Daito, Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai:
1 Gb/s, 50 µm × 50 µm Pads on Board Wireless Connector Based on Track-and-Charge Scheme Allowing Contacted Signaling. IEICE Trans. Electron. 94-C(6): 992-998 (2011) - [j62]Tadashi Yasufuku, Yasumi Nakamura, Piao Zhe, Makoto Takamiya, Takayasu Sakurai:
Power Supply Voltage Dependence of Within-Die Delay Variation of Regular Manual Layout and Irregular Place-and-Route Layout. IEICE Trans. Electron. 94-C(6): 1072-1075 (2011) - [j61]Koichi Ishida, Naoki Masunaga, Ryo Takahashi, Tsuyoshi Sekitani, Shigeki Shino, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
User Customizable Logic Paper (UCLP) With Sea-Of Transmission-Gates (SOTG) of 2-V Organic CMOS and Ink-Jet Printed Interconnects. IEEE J. Solid State Circuits 46(1): 285-292 (2011) - [j60]Lechang Liu, Takayasu Sakurai, Makoto Takamiya:
A Charge-Domain Auto- and Cross-Correlation Based Data Synchronization Scheme With Power- and Area-Efficient PLL for Impulse Radio UWB Receiver. IEEE J. Solid State Circuits 46(6): 1349-1359 (2011) - [j59]Koichi Ishida, Tadashi Yasufuku, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi:
1.8 V Low-Transient-Energy Adaptive Program-Voltage Generator Based on Boost Converter for 3D-Integrated NAND Flash SSD. IEEE J. Solid State Circuits 46(6): 1478-1487 (2011) - [j58]Mutsuo Daito, Yoshiro Nakata, Satoshi Sasaki, Hiroyuki Gomyo, Hideki Kusamitsu, Yoshio Komoto, Kunihiko Iizuka, Katsuyuki Ikeuchi, Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai:
Capacitively Coupled Non-Contact Probing Circuits for Membrane-Based Wafer-Level Simultaneous Testing. IEEE J. Solid State Circuits 46(10): 2386-2395 (2011) - [j57]Yu Pu, Xin Zhang, Katsuyuki Ikeuchi, Atsushi Muramatsu, Atsushi Kawasumi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits. IEEE Trans. Circuits Syst. II Express Briefs 58-II(5): 294-298 (2011) - [c87]Katsuyuki Ikeuchi, Makoto Takamiya, Takayasu Sakurai:
Through Silicon Capacitive Coupling (TSCC) interface for 3D stacked dies. 3DIC 2011: 1-5 - [c86]Xin Zhang, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai:
An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOS. ASP-DAC 2011: 109-110 - [c85]Po-Hung Chen, Koichi Ishida, Xin Zhang, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai:
A 80-mV input, fast startup dual-mode boost converter with charge-pumped pulse generator for energy harvesting. A-SSCC 2011: 33-36 - [c84]Shinichi Moriwaki, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Shinji Miyano:
0.4V SRAM with bit line swing suppression charge share hierarchical bit line scheme. CICC 2011: 1-4 - [c83]Hiroshi Fuketa, Satoshi Iida, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates. DAC 2011: 984-989 - [c82]Atsushi Muramatsu, Tadashi Yasufuku, Masahiro Nomura, Makoto Takamiya, Hirofumi Shinohara, Takayasu Sakurai:
12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains. ESSCIRC 2011: 191-194 - [c81]Tadashi Yasufuku, Satoshi Iida, Hiroshi Fuketa, Koji Hirairi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai:
Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS. ISLPED 2011: 21-26 - [c80]Takayasu Sakurai:
Designing ultra-low voltage logic. ISLPED 2011: 57-58 - [c79]Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics. ISLPED 2011: 163-168 - [c78]Kentaro Honda, Katsuyuki Ikeuchi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai:
Reduction of minimum operating voltage (VDDmin) of CMOS logic circuits with post-fabrication automatically selective charge injection. ISLPED 2011: 175-180 - [c77]Jan M. Rabaey, Hugo De Man, Mark Horowitz, Takayasu Sakurai, Jack Sun, Dan Dobberpuhl, Kiyoo Itoh, Philippe Magarshack, Asad A. Abidi, Hermann Eul:
Beyond the horizon: The next 10x reduction in power - Challenges and solutions. ISSCC 2011: 31 - [c76]Po-Hung Chen, Koichi Ishida, Katsuyuki Ikeuchi, Xin Zhang, Kentaro Honda, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai:
A 95mV-startup step-up converter with Vth-tuned oscillator by fixed-charge programming and capacitor pass-on scheme. ISSCC 2011: 216-218 - [c75]Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Tsuyoshi Sekitani, Hiroyoshi Nakajima, Hiroki Maeda, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
100V AC power meter system-on-a-film (SoF) integrating 20V organic CMOS digital and analog circuits with floating gate for process-variation compensation and 100V organic PMOS rectifier. ISSCC 2011: 218-220 - 2010
- [j56]Tadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi:
Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories. IEICE Trans. Electron. 93-C(3): 317-323 (2010) - [j55]Tadashi Yasufuku, Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai:
Difficulty of Power Supply Voltage Scaling in Large Scale Subthreshold Logic Circuits. IEICE Trans. Electron. 93-C(3): 332-339 (2010) - [j54]Lechang Liu, Zhiwei Zhou, Takayasu Sakurai, Makoto Takamiya:
A 1.76 mW, 100 Mbps Impulse Radio UWB Receiver with Multiple Sampling Correlators Eliminating Need for Phase Synchronization in 65-nm CMOS. IEICE Trans. Electron. 93-C(6): 796-802 (2010) - [j53]Mitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda:
2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking. IEEE J. Solid State Circuits 45(1): 134-141 (2010) - [j52]Koichi Ishida, Naoki Masunaga, Zhiwei Zhou, Tadashi Yasufuku, Tsuyoshi Sekitani, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
Stretchable EMI Measurement Sheet With 8 ˟ 8 Coil Array, 2 V Organic CMOS Decoder, and 0.18 μ m Silicon CMOS LSIs for Electric and Magnetic Field Detection. IEEE J. Solid State Circuits 45(1): 249-259 (2010) - [j51]Youngsoo Shin, Jun Seomun, Kyu-Myung Choi, Takayasu Sakurai:
Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs. ACM Trans. Design Autom. Electr. Syst. 15(4): 28:1-28:37 (2010) - [c74]Koichi Ishida, Koichi Takemura, Kazuhiro Baba, Makoto Takamiya, Takayasu Sakurai:
3D stacked buck converter with 15μm thick spiral inductor on silicon interposer for fine-grain power-supply voltage control in SiP's. 3DIC 2010: 1-4 - [c73]Gil-Su Kim, Katsuyuki Ikeuchi, Mutsuo Daito, Makoto Takamiya, Takayasu Sakurai:
A high-speed, low-power capacitive-coupling transceiver for wireless wafer-level testing systems. 3DIC 2010: 1-4 - [c72]Po-Hung Chen, Koichi Ishida, Xin Zhang, Yasuaki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai:
0.18-V input charge pump with forward body biasing in startup circuit using 65nm CMOS. CICC 2010: 1-4 - [c71]Naoki Masunaga, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai:
EMI Camera LSI (EMcam) with 12 × 4 on-chip loop antenna matrix in 65-nm CMOS to measure EMI noise distribution with 60-µm spatial precision. CICC 2010: 1-4 - [c70]Yasuyuki Okuma, Koichi Ishida, Yoshikatsu Ryu, Xin Zhang, Po-Hung Chen, Kazunori Watanabe, Makoto Takamiya, Takayasu Sakurai:
0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS. CICC 2010: 1-4 - [c69]Makoto Takamiya, Koichi Ishida, Tsuyoshi Sekitani, Takao Someya, Takayasu Sakurai:
Design of large area electronics with organic transistors. ICCAD 2010: 500-503 - [c68]Yu Pu, Xin Zhang, Jim Huang, Atsushi Muramatsu, Masahiro Nomura, Koji Hirairi, Hidehiro Takata, Taro Sakurabayashi, Shinji Miyano, Makoto Takamiya, Takayasu Sakurai:
Misleading energy and performance claims in sub/near threshold digital systems. ICCAD 2010: 625-631 - [c67]Koichi Ishida, Naoki Masunaga, Ryo Takahashi, Tsuyoshi Sekitani, Shigeki Shino, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
User Customizable Logic Paper (UCLP) with organic sea-of-transmission-gates (SOTG) architecture and ink-jet printed interconnects. ISSCC 2010: 138-139 - [c66]Mutsuo Daito, Yoshiro Nakata, Satoshi Sasaki, Hiroyuki Gomyo, Hideki Kusamitsu, Yoshio Komoto, Kunihiko Iizuka, Katsuyuki Ikeuchi, Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai:
Capacitively coupled non-contact probing circuits for membrane-based wafer-level simultaneous testing. ISSCC 2010: 144-145 - [c65]Pascal Urard, Ken Takeuchi, Kerry Bernstein, Hideto Hidaka, Michael Phan, Joo-Sun Choi, Bob Payne, Vladimir Stojanovic, Kees van Berkel, Takayasu Sakurai:
Silicon 3D-integration technology and systems. ISSCC 2010: 510-511 - [c64]Azeez Bhavnagarwala, Shekhar Borkar, Takayasu Sakurai, Siva G. Narendra:
The semiconductor industry in 2025. ISSCC 2010: 534-535
2000 – 2009
- 2009
- [j50]Yasumi Nakamura, Makoto Takamiya, Takayasu Sakurai:
An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise. IEICE Trans. Electron. 92-C(4): 468-474 (2009) - [j49]Lechang Liu, Yoshio Miyamoto, Zhiwei Zhou, Kosuke Sakaida, Jisun Ryu, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai:
A 100 Mbps, 4.1 pJ/bit Threshold Detection-Based Impulse Radio UWB Transceiver in 90 nm CMOS. IEICE Trans. Electron. 92-C(6): 769-776 (2009) - [j48]Makoto Takamiya, Takayasu Sakurai:
Low Power VLSI Circuit Design with Fine-Grain Voltage Engineering. Inf. Media Technol. 4(2): 165-176 (2009) - [j47]Makoto Takamiya, Takayasu Sakurai:
Low Power VLSI Circuit Design with Fine-Grain Voltage Engineering. IPSJ Trans. Syst. LSI Des. Methodol. 2: 18-29 (2009) - [j46]Noriyuki Miura, Yoshinori Kohama, Yasufumi Sugimori, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda:
A High-Speed Inductive-Coupling Link With Burst Transmission. IEEE J. Solid State Circuits 44(3): 947-955 (2009) - [j45]Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai:
A 25-mV-Sensitivity 2-Gb/s Optimum-Logic-Threshold Capacitive-Coupling Receiver for Wireless Wafer Probing Systems. IEEE Trans. Circuits Syst. II Express Briefs 56-II(9): 709-713 (2009) - [j44]Lechang Liu, Makoto Takamiya, Tsuyoshi Sekitani, Yoshiaki Noguchi, Shintaro Nakano, Koichiro Zaitsu, Tadahiro Kuroda, Takao Someya, Takayasu Sakurai:
A 107-pJ/bit 100-kb/s 0.18- muhboxm Capacitive-Coupling Transceiver With Data Edge Signaling and DC Power-Free Pulse Detector for Printable Communication Sheet. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(11): 2511-2518 (2009) - [c63]Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai:
A capacitive coupling interface with high sensitivity for wireless wafer testing. 3DIC 2009: 1-5 - [c62]Tadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi:
Effect of resistance of TSV's on performance of boost converter for low power 3D SSD with NAND flash memories. 3DIC 2009: 1-4 - [c61]Lechang Liu, Yoshio Miyamoto, Zhiwei Zhou, Kosuke Sakaida, Jisun Ryu, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai:
A 100Mbps, 0.19mW asynchronous threshold detector with DC power-free pulse discrimination for impulse UWB receiver. ASP-DAC 2009: 97-98 - [c60]Katsuyuki Ikeuchi, Kosuke Sakaida, Koichi Ishida, Takayasu Sakurai, Makoto Takamiya:
Switched Resonant Clocking (SRC) scheme enabling dynamic frequency scaling and low-speed test. CICC 2009: 33-36 - [c59]Tadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi:
Inductor design of 20-V boost converter for low power 3D solid state drive with NAND flash memories. ISLPED 2009: 87-92 - [c58]Koichi Ishida, Tadashi Yasufuku, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi:
A 1.8V 30nJ adaptive program-voltage (20V) generator for 3D-integrated NAND flash SSD. ISSCC 2009: 238-239 - [c57]Yasufumi Sugimori, Yoshinori Kohama, Mitsuko Saito, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda:
A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking. ISSCC 2009: 244-245 - [c56]Koichi Ishida, Naoki Masunaga, Zhiwei Zhou, Tadashi Yasufuku, Tsuyoshi Sekitani, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
A stretchable EMI measurement sheet with 8×8 coil array, 2V organic CMOS decoder, and -70dBm EMI detection circuits in 0.18¼m CMOS. ISSCC 2009: 472-473 - 2008
- [j43]Noriyuki Miura, Hiroki Ishikuro, Kiichi Niitsu, Takayasu Sakurai, Tadahiro Kuroda:
A 0.14 pJ/b Inductive-Coupling Transceiver With Digitally-Controlled Precise Pulse Shaping. IEEE J. Solid State Circuits 43(1): 285-291 (2008) - [j42]David Levacq, Makoto Takamiya, Takayasu Sakurai:
Backgate Bias Accelerator for sub-100 ns Sleep-to-Active Modes Transition Time. IEEE J. Solid State Circuits 43(11): 2390-2395 (2008) - [c55]Taro Niiyama, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai:
Expected vectorless Teacher-Student Swap (TSS) test method with dual power supply voltages for 0.3V homogeneous multi-core LSI's. CICC 2008: 137-140 - [c54]Yasumi Nakamura, David Levacq, Limin Xiao, Takuya Minakawa, Taro Niiyama, Makoto Takamiya, Takayasu Sakurai:
1/5 power reduction by global optimization based on fine-grained body biasing. CICC 2008: 547-550 - [c53]Takayasu Sakurai:
Solving issues of integrated circuits by 3D-stacking meeting with the era of power, integrity attackers and NRE explosion and a bit of future. ESSCIRC 2008: 10-16 - [c52]Sungdae Choi, Katsuyuki Ikeuchi, Hyunkyung Kim, Kenichi Inagaki, Masami Murakata, Nobuyuki Nishiguchi, Makoto Takamiya, Takayasu Sakurai:
Experimental assessment of logic circuit performance variability with regular fabrics at 90nm technology node. ESSCIRC 2008: 50-53 - [c51]Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai:
Increasing minimum operating voltage (VDDmin) with number of CMOS logic gates and experimental verification with up to 1Mega-stage ring oscillators. ISLPED 2008: 117-122 - [c50]Takayasu Sakurai:
Next-generation power-aware design. ISLPED 2008: 383-384 - [c49]Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai:
Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and its Implications in Low Power DFM. ISQED 2008: 133-136 - [c48]Lechang Liu, Makoto Takamiya, Tsuyoshi Sekitani, Yoshiaki Noguchi, Shintaro Nakano, Koichiro Zaitsu, Tadahiro Kuroda, Takao Someya, Takayasu Sakurai:
A 107pJ/b 100kb/s 0.18μm Capacitive-Coupling Transceiver for Printable Communication Sheet. ISSCC 2008: 292-293 - [c47]Noriyuki Miura, Yoshinori Kohama, Yasufumi Sugimori, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda:
An 11Gb/s Inductive-Coupling Link with Burst Transmission. ISSCC 2008: 298-299 - 2007
- [j41]Fayez Robert Saliba, Hiroshi Kawaguchi, Takayasu Sakurai:
A Self-Alignment Row-by-Row Variable-VDD Scheme Reducing 90% of Active-Leakage Power in SRAM's. IEICE Trans. Electron. 90-C(4): 743-748 (2007) - [j40]Koichi Ishida, Atit Tamtrakarn, Hiroki Ishikuro, Makoto Takamiya, Takayasu Sakurai:
An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors. IEICE Trans. Electron. 90-C(4): 786-792 (2007) - [j39]Kiichi Niitsu, Noriyuki Miura, Mari Inoue, Yoshihiro Nakagawa, Masamoto Tago, Masayuki Mizuno, Takayasu Sakurai, Tadahiro Kuroda:
Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link. IEICE Trans. Electron. 90-C(4): 829-835 (2007) - [j38]Hiroshi Kawaguchi, Danardono Dwi Antono, Takayasu Sakurai:
Closed-Form Expressions for Crosstalk Noise and Worst-Case Delay on Capacitively Coupled Distributed RC Lines. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2669-2681 (2007) - [j37]Makoto Takamiya, Tsuyoshi Sekitani, Yusaku Kato, Hiroshi Kawaguchi, Takao Someya, Takayasu Sakurai:
An Organic FET SRAM With Back Gate to Increase Static Noise Margin and Its Application to Braille Sheet Display. IEEE J. Solid State Circuits 42(1): 93-100 (2007) - [j36]Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi, Takayasu Sakurai, Tadahiro Kuroda:
A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link. IEEE J. Solid State Circuits 42(1): 111-122 (2007) - [j35]Noriyuki Miura, Takayasu Sakurai, Tadahiro Kuroda:
Crosstalk Countermeasures for High-Density Inductive-Coupling Channel Array. IEEE J. Solid State Circuits 42(2): 410-421 (2007) - [j34]Kohei Onizuka, Kenichi Inagaki, Hiroshi Kawaguchi, Makoto Takamiya, Takayasu Sakurai:
Stacked-Chip Implementation of On-Chip Buck Converter for Distributed Power Supply System in SiPs. IEEE J. Solid State Circuits 42(11): 2404-2410 (2007) - [c46]Takayasu Sakurai:
Meeting with the Forthcoming IC Design "The Era of Power, Variability and NRE Explosion and a Bit of the Future". ASP-DAC 2007 - [c45]David Levacq, Takuya Minakawa, Makoto Takamiya, Takayasu Sakurai:
A Wide Range Spatial Frequency Analysis of Intra-Die Variations with 4-mm 4000 × 1 Transistor Arrays in 90nm CMOS. CICC 2007: 257-260 - [c44]David Levacq, Muhammad Yazid, Hiroshi Kawaguchi, Makoto Takamiya, Takayasu Sakurai:
Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power Saving in Clock Distribution. ESSCIRC 2007: 190-193 - [c43]Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda:
A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping. ISSCC 2007: 358-608 - [c42]Makoto Takamiya, Tsuyoshi Sekitani, Yoshio Miyamoto, Yoshiaki Noguchi, Hiroshi Kawaguchi, Takao Someya, Takayasu Sakurai:
Design Solutions for a Multi-Object Wireless Power Transmission Sheet Based on Plastic Switches. ISSCC 2007: 362-609 - [c41]Takayasu Sakurai:
Meeting with the forthcoming IC design. SBCCI 2007: 2 - 2006
- [j33]Canh Quang Tran, Hiroshi Kawaguchi, Takayasu Sakurai:
Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-VTH/VDD and Micro-VDD-Hopping. IEICE Trans. Electron. 89-C(3): 280-286 (2006) - [j32]Daisuke Mizoguchi, Noriyuki Miura, Takayasu Sakurai, Tadahiro Kuroda:
A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology. IEICE Trans. Electron. 89-C(3): 320-326 (2006) - [j31]Danardono Dwi Antono, Kenichi Inagaki, Hiroshi Kawaguchi, Takayasu Sakurai:
Trends of On-Chip Interconnects in Deep Sub-Micron VLSI. IEICE Trans. Electron. 89-C(3): 392-394 (2006) - [j30]Danardono Dwi Antono, Kenichi Inagaki, Hiroshi Kawaguchi, Takayasu Sakurai:
Simple Waveform Model of Inductive Interconnects by Delayed Quadratic Transfer Function with Application to Scaling Trend of Inductive Effects in VLSI's. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3569-3578 (2006) - [j29]Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Takayasu Sakurai, Tadahiro Kuroda:
A 195-gb/s 1.2-W inductive inter-chip wireless superconnect with transmit power control scheme for 3-D-stacked system in a package. IEEE J. Solid State Circuits 41(1): 23-34 (2006) - [j28]Koichi Ishida, Kouichi Kanda, Atit Tamtrakarn, Hiroshi Kawaguchi, Takayasu Sakurai:
Managing subthreshold leakage in charge-based analog circuits with low-VTH transistors by analog T- switch (AT-switch) and super cut-off CMOS (SCCMOS). IEEE J. Solid State Circuits 41(4): 859-867 (2006) - [j27]Kohei Onizuka, Hiroshi Kawaguchi, Makoto Takamiya, Takayasu Sakurai:
$V_rm DD$-Hopping Accelerators for On-Chip Power Supply Circuit to Achieve Nanosecond-Order Transient Time. IEEE J. Solid State Circuits 41(11): 2382-2389 (2006) - [j26]Kyeong-Sik Min, Hun-Dae Choi, H.-Y. Choi, Hiroshi Kawaguchi, Takayasu Sakurai:
Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-VDD LSIs. IEEE Trans. Very Large Scale Integr. Syst. 14(4): 430-435 (2006) - [c40]Koichi Ishida, Atit Tamtrakarn, Takayasu Sakurai:
A 0.5-V sigma-delta modulator using analog T-switch scheme for the subthreshold leakage suppression. ASP-DAC 2006: 98-99 - [c39]Kohei Onizuka, Hiroshi Kawaguchi, Makoto Takamiya, Tadahiro Kuroda, Takayasu Sakurai:
Chip-to-Chip Inductive Wireless Power Transmission System for SiP Applications. CICC 2006: 575-578 - [c38]Atit Tamtrakarn, Hiroki Ishikuro, Koichi Ishida, Takayasu Sakurai:
Compact outside-rail circuit structure by single-cascode two-transistor topology. CICC 2006: 619-622 - [c37]Makoto Takamiya, Tsuyoshi Sekitani, Yusaku Kato, Hiroshi Kawaguchi, Teruki Someya, Takayasu Sakurai:
An Organic FET SRAM for Braille Sheet Display with Back Gate to Increase Static Noise Margin. ISSCC 2006: 1060-1069 - [c36]Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi, Takayasu Sakurai, Tadahiro Kuroda:
A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link. ISSCC 2006: 1676-1685 - 2005
- [j25]Kyeong-Sik Min, Kouichi Kanda, Hiroshi Kawaguchi, Kenichi Inagaki, Fayez Robert Saliba, Hoon-Dae Choi, Hyun-Young Choi, Daejeong Kim, Dong Myong Kim, Takayasu Sakurai:
Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two Orders of Magnitude Leakage Current Reduction of Sub-1-V-VDD SRAM's. IEICE Trans. Electron. 88-C(4): 760-767 (2005) - [j24]Hiroshi Kawaguchi, Takao Someya, Tsuyoshi Sekitani, Takayasu Sakurai:
Cut-and-paste customization of organic FET integrated circuit and its application to electronic artificial skin. IEEE J. Solid State Circuits 40(1): 177-185 (2005) - [j23]Noriyuki Miura, Daisuke Mizoguchi, Takayasu Sakurai, Tadahiro Kuroda:
Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect. IEEE J. Solid State Circuits 40(4): 829-837 (2005) - [j22]Keisuke Toyama, Satoshi Misaka, Kazuo Aisaka, Toshiyuki Aritsuka, Kunio Uchiyama, Koichiro Ishibashi, Hiroshi Kawaguchi, Takayasu Sakurai:
Frequency-voltage cooperative CPU power control: A design rule and its application by feedback prediction. Syst. Comput. Jpn. 36(6): 39-48 (2005) - [j21]Hiroshi Kawaguchi, Youngsoo Shin, Takayasu Sakurai:
μITRON-LP: power-conscious real-time OS based on cooperative voltage scaling for multimedia applications. IEEE Trans. Multim. 7(1): 67-74 (2005) - [c35]Koichi Ishida, Kouichi Kanda, Atit Tamtrakarn, Hiroshi Kawaguchi, Takayasu Sakurai:
Subthreshold-leakage suppressed switched capacitor circuit based on super cut-off CMOS (SCCMOS). ISCAS (4) 2005: 3119-3122 - [c34]Canh Quang Tran, Hiroshi Kawaguchi, Takayasu Sakurai:
More than two orders of magnitude leakage current reduction in look-up table for FPGAs. ISCAS (5) 2005: 4701-4704 - 2004
- [j20]Kouichi Kanda, Hattori Sadaaki, Takayasu Sakurai:
90% write power-saving SRAM using sense-amplifying memory cell. IEEE J. Solid State Circuits 39(6): 927-933 (2004) - [j19]Jin-Hyeok Choi, Yingxue Xu, Takayasu Sakurai:
Statistical leakage current reduction in high-leakage environments using locality of block activation in time domain. IEEE J. Solid State Circuits 39(9): 1497-1503 (2004) - [c33]Takayuki Miyazaki, Canh Quang Tran, Hiroshi Kawaguchi, Takayasu Sakurai:
Observation of one-fifth-of-a-clock wake-up time of power-gated circuit. CICC 2004: 87-90 - [c32]Noriyuki Miura, Daisuke Mizoguchi, Takayasu Sakurai, Tadahiro Kuroda:
Cross talk countermeasures in inductive inter-chip wireless superconnect. CICC 2004: 99-102 - [c31]Takayasu Sakurai:
Low power digital circuit design. ESSCIRC 2004: 11-18 - 2003
- [j18]Hyunsik Im, Takashi Inukai, Hiroyuki Gomyo, Toshiro Hiramoto, Takayasu Sakurai:
VTCMOS characteristics and its optimum conditions predicted by a compact analytical model. IEEE Trans. Very Large Scale Integr. Syst. 11(5): 755-761 (2003) - [c30]Jin-Hyeok Choi, Takayasu Sakurai:
Statistical leakage current reduction by self-timed cut-off scheme for high leakage environments. CICC 2003: 635-638 - [c29]Jan M. Rabaey, Dennis Sylvester, David T. Blaauw, Kerry Bernstein, Jerry Frenkil, Mark Horowitz, Wolfgang Nebel, Takayasu Sakurai, Andrew Yang:
Reshaping EDA for power. DAC 2003: 15 - 2002
- [j17]Seongsoo Lee, Seungjun Lee, Takayasu Sakurai:
Energy-Constrained VDD Hopping Scheme with Run-Time Power Estimation for Low-Power Real-Time VLSI Systems. J. Circuits Syst. Comput. 11(6): 601-620 (2002) - [j16]Koichi Nose, Masayuki Hirabayashi, Hiroshi Kawaguchi, Seongsoo Lee, Takayasu Sakurai:
VTH-hopping scheme to reduce subthreshold leakage for low-power processors. IEEE J. Solid State Circuits 37(3): 413-419 (2002) - [j15]Youngsoo Shin, Takayasu Sakurai:
Power distribution analysis of VLSI interconnects using model orderreduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(6): 739-745 (2002) - [c28]Takayasu Sakurai:
Minimizing power across multiple technology and design levels. ICCAD 2002: 24-27 - [c27]Kyeong-Sik Min, Young-Hee Kim, Jin-Hong Ahn, Jin-Yong Chung, Takayasu Sakurai:
CMOS charge pumps using cross-coupled charge transfer switches with improved voltage pumping gain and low gate-oxide stress for low-voltage memory circuits. ISCAS (5) 2002: 545-548 - [c26]Koichi Nose, Takayasu Sakurai:
Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology. ISLPED 2002: 24-29 - [c25]Takayasu Sakurai:
Low-Power and High-Speed V VLSI Design with Low Supply Voltage through Cooperation between Levels (invited). ISQED 2002: 445-450 - 2001
- [j14]Kouichi Kanda, Kouichi Nose, Hiroshi Kawaguchi, Takayasu Sakurai:
Design impact of positive temperature dependence on drain current in sub-1-V CMOS VLSIs. IEEE J. Solid State Circuits 36(10): 1559-1564 (2001) - [j13]Youngsoo Shin, Kiyoung Choi, Takayasu Sakurai:
Power-conscious Scheduling for Real-time Embedded Systems Design. VLSI Design 12(2): 139-150 (2001) - [c24]Koichi Nose, Masayuki Hirabayashi, Hiroshi Kawaguchi, Seongsoo Lee, Takayasu Sakurai:
VTH-hopping scheme for 82% power saving in low-voltage processors. CICC 2001: 93-96 - [c23]Youngsoo Shin, Hiroshi Kawaguchi, Takayasu Sakurai:
Cooperative voltage scaling (CVS) between OS and applications for low-power real-time systems. CICC 2001: 553-556 - [c22]Youngsoo Shin, Takayasu Sakurai:
Coupling-Driven Bus Design for Low-Power Application-Specific Systems. DAC 2001: 750-753 - [c21]Hiroshi Kawaguchi, Gang Zhang, Seongsoo Lee, Takayasu Sakurai:
An LSI for VDD-hopping and MPEG4 system based on the chip. ISCAS (4) 2001: 918-921 - [c20]Hyunsik Im, Takashi Inukai, Hiroyuki Gomyo, Toshiro Hiramoto, Takayasu Sakurai:
VTCMOS characteristics and its optimum conditions predicted by a compact analytical model. ISLPED 2001: 123-128 - [c19]Takashi Inukai, Toshiro Hiramoto, Takayasu Sakurai:
Variable threshold CMOS (VTCMOS) in series connected circuits. ISLPED 2001: 201-206 - [c18]Masayuki Hirabayashi, Koichi Nose, Takayasu Sakurai:
Design methodology and optimization strategy for dual-VTH scheme using commercially available tools. ISLPED 2001: 283-286 - [c17]Youngsoo Shin, Takayasu Sakurai:
Estimation of power distribution in VLSI interconnects. ISLPED 2001: 370-375 - 2000
- [j12]Hiroshi Kawaguchi, Koichi Nose, Takayasu Sakurai:
A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current. IEEE J. Solid State Circuits 35(10): 1498-1501 (2000) - [j11]Koichi Nose, Takayasu Sakurai:
Analysis and future trend of short-circuit power. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(9): 1023-1030 (2000) - [c16]Seongsoo Lee, Takayasu Sakurai:
Run-time power control scheme using software feedback loop for low-power real-time application. ASP-DAC 2000: 381-386 - [c15]Koichi Nose, Takayasu Sakurai:
Optimization of VDD and VTH for low-power and high speed applications. ASP-DAC 2000: 469-474 - [c14]Nguyen Minh Duc, Takayasu Sakurai:
Compact yet high performance (CyHP) library for short time-to-market with new technologies. ASP-DAC 2000: 475-480 - [c13]Takayasu Sakurai:
Design challenges for 0.1um and beyond: embedded tutorial. ASP-DAC 2000: 553-558 - [c12]Takashi Inukai, Makoto Takamiya, Kouichi Nose, Hiroshi Kawaguchi, Toshiro Hiramoto, Takayasu Sakurai:
Boosted gate MOS (BGMOS): device/circuit cooperation scheme to achieve leakage-free giga-scale integration. CICC 2000: 409-412 - [c11]Seongsoo Lee, Takayasu Sakurai:
Run-time voltage hopping for low-power real-time systems. DAC 2000: 806-809 - [c10]Youngsoo Shin, Kiyoung Choi, Takayasu Sakurai:
Power Optimization of Real-Time Embedded Systems on Variable Speed Processors. ICCAD 2000: 365-368 - [c9]Koichi Nose, Soo-Ik Chae, Takayasu Sakurai:
Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session). ISLPED 2000: 228-230 - [c8]Takayasu Sakurai:
Reducing Power Consumption of CMOS VLSI's through VDD and VTH Control. ISQED 2000: 417-424
1990 – 1999
- 1999
- [c7]Kouichi Kanda, Kouichi Nose, Hiroshi Kawaguchi, Takayasu Sakurai:
Design impact of positive temperature dependence of drain current in sub 1 V CMOS VLSIs. CICC 1999: 563-566 - 1998
- [j10]Tadahiro Kuroda, Kojiro Suzuki, Shinji Mita, Tetsuya Fujita, Fumiyuki Yamane, Fumihiko Sano, Akihiko Chiba, Yoshinori Watanabe, Koji Matsuda, Takeo Maeda, Takayasu Sakurai, Tohru Furuyama:
Variable supply-voltage scheme for low-power high-speed CMOS digital design. IEEE J. Solid State Circuits 33(3): 454-462 (1998) - [j9]Hiroshi Kawaguchi, Takayasu Sakurai:
A reduced clock-swing flip-flop (RCSFF) for 63% power reduction. IEEE J. Solid State Circuits 33(5): 807-811 (1998) - [c6]Hiroshi Kawaguchi, Takayasu Sakurai:
Delay and Noise Formulas for Capacitively Coupled Distributed RC Lines. ASP-DAC 1998: 35-43 - [c5]Koichi Nose, Takayasu Sakurai:
Integrated Current Sensing Device for Micro IDDQ Test. Asian Test Symposium 1998: 323-326 - [c4]Seiji Takeuchi, Takayasu Sakurai:
A fine-grain, current mode scheme for VLSI proximity search engine. ICCD 1998: 184-185 - 1996
- [j8]Akilesh Parameswar, Hiroyuki Hara, Takayasu Sakurai:
A swing restored pass-transistor logic-based multiply and accumulate circuit for multimedia applications. IEEE J. Solid State Circuits 31(6): 804-809 (1996) - [j7]Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Tetsu Nagamatsu, Shinichi Yoshioka, Kojiro Suzuki, Fumihiko Sano, Masayuki Norishima, Masayuki Murota, Makoto Kako, Masaaki Kinugawa, Masakazu Kakurnu, Takayasu Sakurai:
A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme. IEEE J. Solid State Circuits 31(11): 1770-1779 (1996) - [j6]Tadahiro Kuroda, Takayasu Sakurai:
Threshold-Volgage control schemes through substrate-bias for low-power high-speed CMOS LSI design. J. VLSI Signal Process. 13(2-3): 191-201 (1996) - [c3]Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Toshiaki Mori, Kenji Matsuo, Masakazu Kakumu, Takayasu Sakurai:
Substrate noise influence on circuit performance in variable threshold-voltage scheme. ISLPED 1996: 309-312 - 1994
- [j5]Yasuo Unekawa, Tsuguo Kobayashi, Tsukasa Shirotori, Yukihiro Fujimoto, Takayoshi Shimazawa, Kazutaka Nogami, Takehiko Nakao, Kazukiro Sawada, Masataka Matsui, Takayasu Sakurai, Man Kit Tang, William A. Huffman:
A 110-MHz/1-Mb synchronous TagRAM. IEEE J. Solid State Circuits 29(4): 403-410 (1994) - [j4]Masataka Matsui, Hiroyuki Hara, Yoshiharu Uetani, Lee-Sup Kim, Tetsu Nagamatsu, Yoshinori Watanabe, Akihiko Chiba, Kouji Matsuda, Takayasu Sakurai:
A 200 MHz 13 mm2 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme. IEEE J. Solid State Circuits 29(12): 1482-1490 (1994) - 1993
- [c2]Takayasu Sakurai:
High-Speed Circuit Design with Scaled-Down MOSFET's and Low Supply Voltage. ISCAS 1993: 1487-1490 - 1992
- [j3]Takayasu Sakurai, Bill Lin, A. Richard Newton:
Fast simulated diffusion: an optimization algorithm for multiminimum problems and its application to MOSFET model parameter extraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(2): 228-234 (1992)
1980 – 1989
- 1988
- [j2]Kazuhiro Sawada, Takayasu Sakurai, Kazutaka Nogami, Katsuhiko Sato, Tsukasa Shirotori, Masakazu Kakuma, Shigeru Morita, Masaaki Kinugawa, Tetsuya Asami, Kazuhito Narita, Jun-Ichi Matsunaga, Akira Higuchi, Mitsuo Isobe, Tetsuya Iizuka:
A 30- mu A data-retention pseudostatic RAM with virtually static RAM mode. IEEE J. Solid State Circuits 23(1): 12-19 (1988) - [j1]Takayasu Sakurai:
Optimization of CMOS arbiter and synchronizer circuits with submicrometer MOSFETs. IEEE J. Solid State Circuits 23(4): 901-906 (1988) - [c1]Takayasu Sakurai:
CMOS inverter delay and other formulas using alpha -power law MOS model. ICCAD 1988: 74-77
Coauthor Index
[j84] [j82] [j81] [c108] [j79] [c104] [c102] [c101] [c99] [j74] [j73] [j72] [j71] [j70] [j68] [c98] [c93] [c88] [j67] [j66] [j65] [j61] [j59] [c86] [c85] [c76] [c75] [j56] [j55] [j52] [c74] [c72] [c71] [c70] [c69] [c67] [j49] [c62] [c61] [c60] [c59] [c58] [c56] [c55] [c51] [c49] [j40] [j28] [c40] [c38] [c35]
[j96] [j95] [j94] [j93] [j92] [j91] [c123] [c122] [c121] [c120] [j90] [j89] [c119] [j88] [j87] [j86] [c118] [c117] [j85] [c116] [c115] [j84] [c114] [c113] [c112] [c111] [j83] [j82] [j81] [j80] [c110] [c109] [c108] [c107] [j79] [j77] [j76] [c106] [c105] [c104] [c103] [c102] [c101] [c100] [c99] [j75] [j74] [j73] [j72] [j71] [j70] [j69] [j68] [c98] [c97] [c96] [c95] [c94] [c93] [c92] [c90] [c88] [j67] [j66] [j65] [j64] [j63] [j62] [j61] [j60] [j59] [j58] [j57] [c87] [c86] [c85] [c83] [c82] [c81] [c79] [c78] [c76] [c75] [j56] [j55] [j54] [j52] [c74] [c73] [c72] [c71] [c70] [c69] [c68] [c67] [c66] [j50] [j49] [j48] [j47] [j45] [j44] [c63] [c62] [c61] [c60] [c59] [c58] [c56] [j42] [c55] [c54] [c52] [c51] [c49] [c48] [j40] [j37] [j34] [c45] [c44] [c42] [j27] [c39] [c37] [c12]
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-11-06 20:28 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
