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ORCIDKenichi Osada
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2010 – 2019
- 2015
[c17]Takashi Takemoto, Yasunobu Matsuoka, Yoshikazu Sugiyama, Hidenori Yonezawa, Hiroki Yamashita, Koichiro Adachi, Takahiro Nakamura, Etsuko Nomoto, Kouji Nakahara, Hideo Arimoto, Kenichi Osada, Tatemi Ido:
A 50-Gb/s NRZ-modulated optical transmitter based on a DFB-LD and a 0.18-µm SiGe BiCMOS LD driver. OFC 2015: 1-3- 2013
- [c16]Yasuhiro Shinozuka, Hiroshi Fuketa, Koichi Ishida, Futoshi Furuta, Kenichi Osada, Kenichi Takeda, Makoto Takamiya, Takayasu Sakurai:
Reducing IR drop in 3D integration to less than 1/4 using Buck Converter on Top die (BCT) scheme. ISQED 2013: 210-215 - 2012
- [c15]Kiyoto Ito
, Makoto Saen, Kenichi Osada:
Scalable robotic-hand control system based on a hierarchical multi-processor architecture adopting a large number of tactile sensors. IROS 2012: 14-19 - [c14]Ming Liu, Tatsuo Nakagawa, Kenichi Osada:
Fully digital voltage-mode control based on predictive hysteresis method (FDVC-PH) for DC-DC converters. ISCAS 2012: 448-451 - 2011
- [j11]Kiichi Niitsu, Yasufumi Sugimori, Yoshinori Kohama, Kenichi Osada, Naohiko Irie, Hiroki Ishikuro, Tadahiro Kuroda:
Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration. IEEE Trans. Very Large Scale Integr. Syst. 19(10): 1902-1907 (2011) - [c13]Futoshi Furuta, Kenichi Osada:
6 Tbps/W, 1 Tbps/mm2, 3D interconnect using adaptive timing control and low capacitance TSV. 3DIC 2011: 1-4 - [e1]Naehyuck Chang, Hiroshi Nakamura, Koji Inoue, Kenichi Osada, Massimo Poncino:
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011, Fukuoka, Japan, August 1-3, 2011. IEEE/ACM 2011, ISBN 978-1-61284-660-6 [contents] - 2010
- [j10]Makoto Saen, Kenichi Osada, Yasuyuki Okuma, Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda:
3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link. IEEE J. Solid State Circuits 45(4): 856-862 (2010) - [j9]Kiichi Niitsu, Yoshinori Kohama, Yasufumi Sugimori, Kazutaka Kasuga, Kenichi Osada, Naohiko Irie, Hiroki Ishikuro, Tadahiro Kuroda:
Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration. IEEE Trans. Very Large Scale Integr. Syst. 18(8): 1238-1243 (2010) - [c12]Kiyoto Ito, Makoto Saen, Kenichi Osada, Tomoyuki Kodama, Hiroyuki Mizuno:
Hierarchical 3D interconnection architecture with tightly-coupled processor-memory integration. 3DIC 2010: 1-6 - [c11]Naoto Miyamoto, Yohei Matsumoto, Hanpei Koike, Tadayuki Matsumura, Kenichi Osada, Yaoko Nakagawa, Tadahiro Ohmi:
Development of a CAD tool for 3D-FPGAs. 3DIC 2010: 1-6
2000 – 2009
- 2009
- [c10]Shigenobu Komatsu, Masanao Yamaoka, Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki, Kenichi Osada:
A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation. CICC 2009: 701-704 - [c9]Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Makoto Saen, Shigenobu Komatsu, Kenichi Osada, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda:
An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM. ISSCC 2009: 480-481 - 2008
- [j8]Kiyoo Itoh, Hideaki Kurata, Kenichi Osada, Tomonori Sekiguchi:
Memory at VLSI Circuits Symposium. IEEE J. Solid State Circuits 43(4): 762-768 (2008) - [c8]Masanao Yamaoka, Kenichi Osada, Takayuki Kawahara:
A cell-activation-time controlled SRAM for low-voltage operation in DVFS SoCs using dynamic stability analysis. ESSCIRC 2008: 286-289 - [c7]Masanao Yamaoka, Noriaki Maeda, Yasuhisa Shimazaki, Kenichi Osada:
65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS. ISSCC 2008: 384-385 - 2007
- [c6]Makoto Saen, Kenichi Osada, Satoshi Misaka, Tetsuya Yamada, Yoshitaka Tsujimoto, Yuki Kondo, Tatsuya Kamei, Yutaka Yoshida, Ei Nagahama, Yusuke Nitta, Takayasu Ito, Tadashi Kameyama, Naohiko Irie:
Embedded SoC Resource Manager to Control Temperature and Data Bandwidth. ISSCC 2007: 296-604 - [c5]Satoru Hanzawa, Naoki Kitai, Kenichi Osada, Akira Kotabe, Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura, Masahiro Moniwa, Takayuki Kawahara:
A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current. ISSCC 2007: 474-616 - 2005
- [j7]Masanao Yamaoka, Yoshihiro Shinozaki, Noriaki Maeda, Yasuhisa Shimazaki, Kei Kato, Shigeru Shimada, Kazumasa Yanagisawa, Kenichi Osada:
A 300-MHz 25-μA/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor. IEEE J. Solid State Circuits 40(1): 186-194 (2005) - [j6]Akira Kotabe, Kenichi Osada, Naoki Kitai, Mio Fujioka, Shiro Kamohara, Masahiro Moniwa, Sadayuki Morita, Yoshikazu Saitoh:
A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme. IEEE J. Solid State Circuits 40(4): 870-876 (2005) - [c4]Kenichi Osada, Takayuki Kawahara, Riichiro Takemura, Naoki Kitai, Norikatsu Takaura, Nozomu Matsuzaki, Kenzo Kurotsuchi, Hiroshi Moriya, Masahiro Moniwa:
Phase change RAM operated with 1.5-V CMOS as low cost embedded memory. CICC 2005: 431-434 - 2004
- [j5]Kenichi Osada, Ken Yamaguchi, Yoshikazu Saitoh, Takayuki Kawahara:
SRAM immunity to cosmic-ray-induced multierrors based on analysis of an induced parasitic bipolar effect. IEEE J. Solid State Circuits 39(5): 827-833 (2004) - [j4]Masanao Yamaoka, Kenichi Osada, Koichiro Ishibashi:
0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme. IEEE J. Solid State Circuits 39(6): 934-940 (2004) - [c3]Kiyoo Itoh, Kenichi Osada, Takayda Kawahara:
Reviews and future prospects of low-voltage embedded RAMs. CICC 2004: 339-344 - [c2]Kenichi Osada, Naoki Kitai, Shiro Kamohara, Takayuki Kawahara:
Analysis of SRAM neutron-induced errors based on the consideration of both charge-collection and parasitic-bipolar failure modes. CICC 2004: 357-360 - [c1]Kiyoo Itoh, Kenichi Osada, Takayuki Kawahara:
Low-Voltage Embedded RAMs - Current Status and Future Trends. PATMOS 2004: 3-15 - 2003
- [j3]Kenichi Osada, Yoshikazu Saitoh, Eishi Ibe, Koichiro Ishibashi:
16.7-fA/cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-ray-induced multierrors. IEEE J. Solid State Circuits 38(11): 1952-1957 (2003) - 2001
- [j2]Kenichi Osada, Jinuk Luke Shin, Masood Khan, Yude Liou, Karl Wang, Kenichi Shoji, Kenichi Kuroda, Shuji Ikeda, Koichiro Ishibashi:
Universal-Vdd 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell. IEEE J. Solid State Circuits 36(11): 1738-1744 (2001)
1990 – 1999
- 1996
- [j1]Hiroyuki Mizuno, Nozomu Matsuzaki, Kenichi Osada, Toshinobu Shinbo, Nagatoshi Ohki, Hiroshi Ishida, Koichiro Ishibashi, Tokuo Kure:
A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators. IEEE J. Solid State Circuits 31(11): 1618-1624 (1996)
Coauthor Index
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