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2020 – today
- 2024
[c10]Victor Moroz, Xiaopeng Xu, Alexei Svizhenko, Xi-Wei Lin, Sergey Popov, Henry Sheng, Kenneth Larsen:
3DIC System-Technology Co-Optimization with a Focus on the Interplay of Thermal, Power, Timing, and Stress Effects. VLSI Technology and Circuits 2024: 1-2- 2023
- [c9]Victor Moroz
:
Gate-All-Around Technology is Coming.: What's Next After GAA? ISPD 2023: 81 - [c8]Victor Moroz, Alexei Svizhenko, Munkang Choi, Plamen Asenov, Jaehyun Lee:
Exploring Power Savings of Gate-All-Around Cryogenic Technology. VLSI Technology and Circuits 2023: 1-2
2010 – 2019
- 2018
- [j2]Paul Pfäffli, Hiu Yung Wong, X. Xu, Luca Silvestri, X. W. Lin, T. Yang, Ravi Tiwari, Souvik Mahapatra, Steve Motzny, Victor Moroz, Terry Ma:
TCAD modeling for reliability. Microelectron. Reliab. 88-90: 1083-1089 (2018) - 2016
- [c7]Jin-Woo Han, Victor Moroz, Andrey Kucherov, Dinesh Maheshwari, Valentin Abramzon, Zvi Or-Bach, Yoshio Nishi, Yuniarto Widjaja:
A CMOS-compatible boosted transistor having >2× drive current and low leakage current. ESSDERC 2016: 214-217 - [c6]Victor Moroz:
Technology Inflection Points. ISPD 2016: 55 - [c5]Victor Moroz, Joanne Huang, Reza Arghavani:
Transistor design for 5nm and beyond: Slowing down electrons to speed up transistors. ISQED 2016: 278-283 - 2010
- [j1]Xi-Wei Lin, Victor Moroz:
Layout Proximity Effects and Modeling Alternatives for IC Designs. IEEE Des. Test Comput. 27(2): 18-25 (2010)
2000 – 2009
- 2009
- [c4]Aditya P. Karmarkar, Xiaopeng Xu, Victor Moroz, Greg Rollins, Xiao Lin:
Analysis of performance and reliability trade-off in dummy pattern design for 32-nm technology. ISQED 2009: 185-189 - 2006
- [c3]Sridhar Tirumala, Yuri Mahotin, Xiao Lin, Victor Moroz, Lee Smith, S. Krishnamurthy, L. Bomholt, Dipu Pramanik:
Bringing Manufacturing into Design via Process-Dependent SPICE Models. ISQED 2006: 801-806 - [c2]Victor Moroz, Lee Smith, Xi-Wei Lin, Dipu Pramanik, Greg Rollins:
Stress-Aware Design Methodology. ISQED 2006: 807-812
1990 – 1999
- 1998
- [c1]Dan Wake, Klas Lilja, Victor Moroz:
A Hybrid Mesh Generation Method for Two and Three Dimensional Simulation of Semiconductor Processes and Devices. IMR 1998: 159-165
Coauthor Index
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