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2020 – today
- 2024
[c28]Roukoz Nabhan, Jean-Max Dutertre, Jean-Baptiste Rigaud, Jean-Luc Danger, Laurent Sauvage:
EM Fault Injection-Induced Clock Glitches: From Mechanism Analysis to Novel Sensor Design. IOLTS 2024: 1-7- [i7]Maxime Spyropoulos, David Vigilant, Fabrice Perion, Renaud Pacalet, Laurent Sauvage:
Masked Vector Sampling for HQC. IACR Cryptol. ePrint Arch. 2024: 1106 (2024) - 2023
- [c27]Roukoz Nabhan, Jean-Max Dutertre, Jean-Baptiste Rigaud
, Jean-Luc Danger, Laurent Sauvage:
Highlighting Two EM Fault Models While Analyzing a Digital Sensor Limitations. DATE 2023: 1-2 - [c26]Roukoz Nabhan, Jean-Max Dutertre, Jean-Baptiste Rigaud, Jean-Luc Danger, Laurent Sauvage:
A Tale of Two Models: Discussing the Timing and Sampling EM Fault Injection Models. FDTC 2023: 1-12 - [c25]Arnaud Varillon, Laurent Sauvage, Jean-Luc Danger:
High-Order Collision Attack Vulnerabilities in Montgomery Ladder Implementations of RSA. SPACE 2023: 139-161 - [i6]Yohaï-Eliel Berreby, Laurent Sauvage:
Investigating Efficient Deep Learning Architectures For Side-Channel Attacks on AES. CoRR abs/2309.13170 (2023) - [i5]Pierre-Augustin Berthet, Cédric Tavernier, Jean-Luc Danger, Laurent Sauvage:
Quasi-linear Masking to Protect Kyber against both SCA and FIA. IACR Cryptol. ePrint Arch. 2023: 1220 (2023) - 2021
- [c24]Sofiane Takarabt, Sylvain Guilley, Youssef Souissi, Khaled Karray, Laurent Sauvage, Yves Mathieu:
Formal Evaluation and Construction of Glitch-resistant Masked Functions. HOST 2021: 304-313 - 2020
- [c23]Oualid Trabelsi, Laurent Sauvage, Jean-Luc Danger:
Characterization of Electromagnetic Fault Injection on a 32-bit Microcontroller Instruction Buffer. AsianHOST 2020: 1-6
2010 – 2019
- 2019
- [c22]Sofiane Takarabt, Alexander Schaub, Adrien Facon, Sylvain Guilley, Laurent Sauvage, Youssef Souissi, Yves Mathieu:
Cache-Timing Attacks Still Threaten IoT Devices. C2SI 2019: 13-30 - 2018
- [c21]Sofiane Takarabt, Kais Chibani, Adrien Facon, Sylvain Guilley, Yves Mathieu, Laurent Sauvage, Youssef Souissi:
Pre-silicon Embedded System Evaluation as New EDA Tool for Security Verification. IVSW 2018: 74-79 - 2017
- [j7]Laurent Sauvage, Tarik Graba, Thibault Porteboeuf:
Multi-level formal verification - A new approach against fault injection attack. J. Cryptogr. Eng. 7(1): 87-95 (2017) - [i4]Wei Cheng, Chao Zheng, Yuchen Cao, Yongbin Zhou, Hailong Zhang, Sylvain Guilley, Laurent Sauvage:
How Far Can We Reach? Breaking RSM-Masked AES-128 Implementation Using Only One Trace. IACR Cryptol. ePrint Arch. 2017: 1144 (2017) - 2016
- [c20]Wei Cheng, Yongbin Zhou, Laurent Sauvage:
Differential Fault Analysis on Midori. ICICS 2016: 307-317 - [c19]Kazuhide Fukushima, Youssef Souissi, Seira Hidano, Robert Nguyen, Jean-Luc Danger, Sylvain Guilley, Yuto Nakano, Shinsaku Kiyomoto, Laurent Sauvage:
Delay PUF Assessment Method Based on Side-Channel and Modeling Analyzes: The Final Piece of All-in-One Assessment Methodology. Trustcom/BigDataSE/ISPA 2016: 201-207 - 2015
- [c18]Lionel Rivière, Zakaria Najm, Pablo Rauzy, Jean-Luc Danger, Julien Bringer, Laurent Sauvage:
High precision fault injections on the instruction cache of ARMv7-M architectures. HOST 2015: 62-67 - [i3]Lionel Rivière, Zakaria Najm, Pablo Rauzy, Jean-Luc Danger, Julien Bringer, Laurent Sauvage:
High Precision Fault Injections on the Instruction Cache of ARMv7-M Architectures. CoRR abs/1510.01537 (2015) - [i2]Lionel Rivière, Zakaria Najm, Pablo Rauzy, Jean-Luc Danger, Julien Bringer, Laurent Sauvage:
High Precision Fault Injections on the Instruction Cache of ARMv7-M Architectures. IACR Cryptol. ePrint Arch. 2015: 147 (2015) - 2014
- [j6]Christophe Clavier, Jean-Luc Danger, Guillaume Duc, M. Abdelaziz Elaabid, Benoît Gérard, Sylvain Guilley, Annelie Heuser, Michael Kasper, Yang Li, Victor Lomné, Daisuke Nakatsu, Kazuo Ohta, Kazuo Sakiyama, Laurent Sauvage, Werner Schindler, Marc Stöttinger, Nicolas Veyrat-Charvillon, Matthieu Walle, Antoine Wurcker:
Practical improvements of side-channel attacks on AES: feedback from the 2nd DPA contest. J. Cryptogr. Eng. 4(4): 259-274 (2014) - [c17]Yuto Nakano, Youssef Souissi, Robert Nguyen, Laurent Sauvage, Jean-Luc Danger, Sylvain Guilley, Shinsaku Kiyomoto, Yutaka Miyake:
A Pre-processing Composition for Secret Key Recovery on Android Smartphone. WISTP 2014: 76-91 - [i1]Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Xuan Thuy Ngo, Laurent Sauvage:
Hardware Trojan Horses in Cryptographic IP Cores. IACR Cryptol. ePrint Arch. 2014: 750 (2014) - 2013
- [c16]Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Xuan Thuy Ngo, Laurent Sauvage:
Hardware Trojan Horses in Cryptographic IP Cores. FDTC 2013: 15-29 - 2012
- [j5]Laurent Sauvage, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu:
Blind Cartography for Side Channel Attacks: Cross-Correlation Cartography. Int. J. Reconfigurable Comput. 2012: 360242:1-360242:9 (2012) - [c15]Taoufik Chouta, Jean-Luc Danger, Laurent Sauvage, Tarik Graba:
A Small and High-Performance Coprocessor for Fingerprint Match-on-Card. DSD 2012: 915-922 - 2011
- [c14]Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane, Denis Réal:
Performance evaluation of protocols resilient to physical attacks. HOST 2011: 51-56 - 2010
- [j4]Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu:
Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics. Int. J. Reconfigurable Comput. 2010: 375245:1-375245:12 (2010) - [j3]Sylvain Guilley, Laurent Sauvage, Florent Flament, Vinh-Nga Vong, Philippe Hoogvorst, Renaud Pacalet:
Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics. IEEE Trans. Computers 59(9): 1250-1263 (2010) - [c13]Shivam Bhasin, Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger:
Unrolling Cryptographic Circuits: A Simple Countermeasure Against Side-Channel Attacks. CT-RSA 2010: 195-207 - [c12]Olivier Meynard, Sylvain Guilley, Jean-Luc Danger, Laurent Sauvage:
Far Correlation-based EMA with a precharacterized leakage model. DATE 2010: 977-980 - [c11]Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane:
Fault Injection Resilience. FDTC 2010: 51-65 - [c10]Sylvain Guilley, Laurent Sauvage, Julien Micolod, Denis Réal, Frédéric Valette:
Defeating Any Secret Cryptography with SCARE Attacks. LATINCRYPT 2010: 273-293 - [c9]Laurent Sauvage, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu:
Cross-Correlation Cartography. ReConFig 2010: 268-273
2000 – 2009
- 2009
- [j2]Laurent Sauvage, Sylvain Guilley, Yves Mathieu:
Electromagnetic Radiations of FPGAs: High Spatial Resolution Cartography and Attack on a Cryptographic Module. ACM Trans. Reconfigurable Technol. Syst. 2(1): 4:1-4:24 (2009) - [c8]Laurent Sauvage, Sylvain Guilley, Jean-Luc Danger, Yves Mathieu, Maxime Nassar:
Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints. DATE 2009: 640-645 - [c7]Sylvain Guilley, Sumanta Chaudhuri, Laurent Sauvage, Jean-Luc Danger, Taha Beyrouthy, Laurent Fesquet:
Updates on the potential of clock-less logics to strengthen cryptographic circuits against side-channel attacks. ICECS 2009: 351-354 - [c6]Shivam Bhasin, Jean-Luc Danger, Florent Flament, Tarik Graba, Sylvain Guilley, Yves Mathieu, Maxime Nassar, Laurent Sauvage, Nidhal Selmane:
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow. ReConFig 2009: 213-218 - [c5]Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu:
DPL on Stratix II FPGA: What to Expect?. ReConFig 2009: 243-248 - 2008
- [j1]Sylvain Guilley, Laurent Sauvage, Philippe Hoogvorst, Renaud Pacalet, Guido Marco Bertoni, Sumanta Chaudhuri:
Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks. IEEE Trans. Computers 57(11): 1482-1497 (2008) - [c4]Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane, Renaud Pacalet:
Silicon-level Solutions to Counteract Passive and Active Attacks. FDTC 2008: 3-17 - [c3]Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Philippe Hoogvorst:
Area optimization of cryptographic co-processors implemented in dual-rail with precharge positive logic. FPL 2008: 161-166 - [c2]Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Laurent Sauvage, Philippe Hoogvorst, Maxime Nassar, Tarik Graba, Vinh-Nga Vong:
Place-and-Route Impact on the Security of DPL Designs in FPGAs. HOST 2008: 26-32 - [c1]Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Tarik Graba, Yves Mathieu:
Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs. SSIRI 2008: 16-23
Coauthor Index
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last updated on 2024-10-07 21:24 CEST by the dblp team
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