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ORCIDStanislav G. Sedukhin
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2020 – today
- 2022
[j13]Stanislav Sedukhin, Yoichi Tomioka
, Kohei Yamamoto:
In Search of the Performance- and Energy-Efficient CNN Accelerators. IEICE Trans. Electron. 105-C(6): 209-221 (2022)- [c47]Kazuya Matsumoto, Yoichi Tomioka, Stanislav Sedukhin:
High Performance Software Systolic Array Computing of Multi-channel Convolution on a GPU. ICCSA (1) 2022: 298-309 - 2021
- [c46]Stanislav Sedukhin, Yoichi Tomioka, Kohei Yamamoto:
In Search of the Performance- and Energy-Efficient CNN Accelerators. COOL CHIPS 2021: 1-6
2010 – 2019
- 2019
- [c45]Stanislav Sedukhin, Kazuya Matsumoto, Yoichi Tomioka:
Brain-inspired Co-design of Algorithm/Architecture for CNN Accelerators. IIAI-AAI 2019: 556-560 - 2018
- [j12]Fumiya Kono, Naohito Nakasato, Kensaku Hayashi, Alexander Vazhenin, Stanislav Sedukhin:
Evaluations of OpenCL-written tsunami simulation on FPGA and comparison with GPU implementation. J. Supercomput. 74(6): 2747-2775 (2018) - 2017
- [c44]Fumiya Kono, Naohito Nakasato, Kensaku Hayashi, Alexander Vazhenin, Stanislav G. Sedukhin:
Performance Evaluation of Tsunami Simulation Using OpenCL on GPU and FPGA. MCSoC 2017: 106-113 - 2016
- [c43]Kohei Nagasu, Kentaro Sano, Fumiya Kono, Naohito Nakasato, Alexander Vazhenin, Stanislav G. Sedukhin:
Parallelism for High-Performance Tsunami Simulation with FPGA: Spatial or Temporal? FCCM 2016: 30 - 2015
- [j11]Kentaro Sano, Fumiya Kono, Naohito Nakasato, Alexander Vazhenin, Stanislav Sedukhin:
Stream Computation of Shallow Water Equation Solver for FPGA-based 1D Tsunami Simulation. SIGARCH Comput. Archit. News 43(4): 82-87 (2015) - 2014
- [j10]Maria Ganzha, Marcin Paprzycki, Stanislav Sedukhin:
Image scrambling on a "mesh-of-tori" architecture. Scalable Comput. Pract. Exp. 15(1) (2014) - [j9]Maria Ganzha, Marcin Paprzycki, Stanislav G. Sedukhin:
Generalized Matrix Multiplication and its Object Oriented Model. Scalable Comput. Pract. Exp. 15(2) (2014) - [c42]Ivan Lirkov, Marcin Paprzycki, Maria Ganzha, Stanislav Sedukhin, Pawel Gepner:
Performance analysis of scalable algorithms for 3D linear transforms. FedCSIS 2014: 613-622 - 2013
- [c41]Maria Ganzha, Marcin Paprzycki, Stanislav Sedukhin:
Library for Matrix Multiplication-based Data Manipulation on a "Mesh-of-Tori" Architecture. FedCSIS 2013: 455-462 - 2012
- [j8]Kazuya Matsumoto, Naohito Nakasato, Stanislav G. Sedukhin:
Blocked United Algorithm for the All-Pairs Shortest Paths Problem on Hybrid CPU-GPU Systems. IEICE Trans. Inf. Syst. 95-D(12): 2759-2768 (2012) - [c40]Kazuya Matsumoto, Naohito Nakasato, Stanislav G. Sedukhin:
Implementing a Code Generator for Fast Matrix Multiplication in OpenCL on the GPU. MCSoC 2012: 198-204 - [c39]Kazuya Matsumoto, Naohito Nakasato, Stanislav G. Sedukhin:
Performance Tuning of Matrix Multiplication in OpenCL on Different GPUs and CPUs. SC Companion 2012: 396-405 - 2011
- [j7]Yuki Ikegaki, Toshiaki Miyazaki, Stanislav G. Sedukhin:
3D-DCT Processor and Its FPGA Implementation. IEICE Trans. Inf. Syst. 94-D(7): 1409-1418 (2011) - [c38]Maria Ganzha, Stanislav Sedukhin, Marcin Paprzycki:
Object Oriented Model of Generalized Matrix Multipication. FedCSIS 2011: 439-442 - [c37]Kazuya Matsumoto, Naohito Nakasato, Stanislav G. Sedukhin:
Blocked All-Pairs Shortest Paths Algorithm for Hybrid CPU-GPU System. HPCC 2011: 145-152 - [c36]Abhijeet A. Ravankar, Stanislav G. Sedukhin:
An O(n) Time-Complexity Matrix Transpose on Torus Array Processor. ICNC 2011: 242-247 - [c35]Stanislav G. Sedukhin, Marcin Paprzycki:
Generalizing Matrix Multiplication for Efficient Computations on Modern Computers. PPAM (1) 2011: 225-234 - [c34]Kazuya Matsumoto, Naohito Nakasato, Tomoya Sakai, Hideki Yahagi, Stanislav G. Sedukhin:
Multi-level Optimization of Matrix Multiplication for GPU-equipped Systems. ICCS 2011: 342-351 - 2010
- [j6]Stanislav G. Sedukhin, Toshiaki Miyazaki, Kenichi Kuroda:
Orbital Systolic Algorithms and Array Processors for Solution of the Algebraic Path Problem. IEICE Trans. Inf. Syst. 93-D(3): 534-541 (2010) - [c33]Stanislav G. Sedukhin, Toshiaki Miyazaki:
Rapid*Closure: Algebraic Extensions of a Scalar Multiply-add Operation. CATA 2010: 19-24 - [c32]Kazuya Matsumoto, Stanislav G. Sedukhin:
Matrix Multiply-Add in Min-plus Algebra on a Short-Vector SIMD Processor of Cell/B.E.. ICNC 2010: 272-274 - [c31]Abhijeet A. Ravankar, Stanislav G. Sedukhin:
Mesh-of-Tori: A Novel Interconnection Network for Frontal Plane Cellular Processors. ICNC 2010: 281-284 - [c30]Stanislav G. Sedukhin, Ahmed Sherif Zekri, Toshiaki Miyazaki:
Orbital Algorithms and Unified Array Processor for Computing 2D Separable Transforms. ICPP Workshops 2010: 127-134
2000 – 2009
- 2009
- [j5]Kazuya Matsumoto, Stanislav G. Sedukhin:
A Solution of the All-Pairs Shortest Paths Problem on the Cell Broadband Engine Processor. IEICE Trans. Inf. Syst. 92-D(6): 1225-1231 (2009) - [c29]Shodai Yokoyama, Kazuya Matsumoto, Stanislav G. Sedukhin:
Matrix Inversion on the Cell/B.E. Processor. HPCC 2009: 148-153 - 2008
- [j4]Ahmed Sherif Zekri, Stanislav G. Sedukhin:
Level-3 BLAS and LU Factorization on a Matrix Processor. Inf. Media Technol. 3(2): 285-300 (2008) - [c28]Toshiaki Miyazaki, Yusuke Nomoto, Yuka Sato, Stanislav G. Sedukhin:
Array processor featuring an effective FIFO-based data stream management. CIT 2008: 255-260 - [c27]Ahmed Sherif Zekri, Stanislav G. Sedukhin:
2-D Separable Transforms on a Matrix Processor. CAINE 2008: 106-111 - 2007
- [c26]Ahmed Sherif Zekri, Stanislav G. Sedukhin:
Evaluating the Performance of Basic Linear Algebra Subroutines on a Torus Array Processor. CIT 2007: 300-305 - [c25]Ahmed Sherif Zekri, Stanislav G. Sedukhin:
Fine-grained Matrix Multiply-Add on a Torus Array Processor. CATA 2007: 44-51 - [c24]Ahmed Sherif Zekri, Stanislav G. Sedukhin:
Performance Evaluation of Basic Linear Algebra Subroutines on a Matrix Co-processor. PPAM 2007: 1190-1199 - 2006
- [c23]Ahmed Sherif Zekri, Stanislav G. Sedukhin:
Matrix Transpose on 2D Torus Array Processor. CIT 2006: 45 - [c22]Ahmed Sherif Zekri, Stanislav G. Sedukhin:
The general matrix multiply-add operation on 2D torus. IPDPS 2006 - 2005
- [j3]Mostafa I. Soliman, Stanislav Sedukhin:
Performance Evaluation of Blas on the Trident Processor. Parallel Process. Lett. 15(4): 407-414 (2005) - [c21]Stanislav Sedukhin, Mostafa I. Soliman:
A Matrix Processor for Math-intensive Applications. CAINE 2005: 109-114 - [c20]Akihito Takahashi, Stanislav Sedukhin:
Parallel Blocked Algorithm for Solving the Algebraic Path Problem on a Matrix Processor. HPCC 2005: 786-795 - [c19]Ahmed Sherif Zekri, Stanislav G. Sedukhin:
Computationally Efficient Parallel Matrix-Matrix Multiplication on the Torus. ISHPC 2005: 219-226 - 2003
- [j2]Mostafa I. Soliman, Stanislav G. Sedukhin:
Matrix Bidiagonalization: Implementation and Evaluation on the Trident Processor. Neural Parallel Sci. Comput. 11(4): 395-422 (2003) - [c18]Mostafa I. Soliman, Stanislav Sedukhin:
BLAS on the Trident Processor: Implementation and Performance Evaluation. CATA 2003: 359-364 - [c17]Mostafa I. Soliman, Stanislav Sedukhin:
Matrix Bidiagonalization on the Trident Processor. IPDPS 2003: 257 - [c16]Stanislav Sedukhin, Mostafa I. Soliman:
Trident: Technology-Scalable Architecture for Data Parallel Application. IPDPS 2003: 264 - [c15]Akihito Takahashi, Mostafa I. Soliman, Stanislav Sedukhin:
Parallel LU-decomposition on Pentium Streaming SIMD Extensions. ISHPC 2003: 423-430 - [e1]Amos Omondi, Stanislav Sedukhin:
Advances in Computer Systems Architecture, 8th Asia-Pacific Conference, ACSAC 2003, Aizu-Wakamatsu, Japan, September 23-26, 2003, Proceedings. Lecture Notes in Computer Science 2823, Springer 2003, ISBN 3-540-20122-X [contents] - 2002
- [c14]Mostafa I. Soliman, Stanislav Sedukhin:
Performance Analysis of SVD Algorithm on the Trident Processor. CW 2002: 95-104 - [c13]Mostafa I. Soliman, Stanislav Sedukhin:
A Multi-level ISA Processor for Accelerating Data Parallel Applications. PDPTA 2002: 1492-1498 - 2001
- [c12]Vladimir V. Savchenko, Stanislav Sedukhin:
Pattern Dependent Reconstruction of Raster Digital Elevation Models from Contour Maps. VIIP 2001: 237-244 - 2000
- [c11]Shietung Peng, Stanislav Sedukhin:
Design of Multi-dimensional DCT Array Processors for Video Applications. Euro-Par 2000: 1086-1094 - [c10]T. Takigahira, Stanislav Sedukhin:
Performance Evaluation of the Clustered Web Server. PDPTA 2000
1990 – 1999
- 1999
- [c9]Shietung Peng, Stanislav Sedukhin, Hiroshi Nagata:
A new scalable array processor for two-dimensional discrete Fourier transform. PARCO 1999: 358-365 - [c8]Shietung Peng, Stanislav Sedukhin, Hiroshi Nagata:
Design Of I/O Efficient, Scalable Array Processors for Multi-dimensional DFT. PDPTA 1999: 1544-1550 - 1997
- [c7]Stanislav Sedukhin, Igor S. Sedukhin:
An Interactive Graphic Tool for Systematic Design and Analysis of VLSI Array Processors. PDPTA 1997: 41-49 - 1996
- [j1]Shietung Peng, Stanislav Sedukhin:
Array Processors Design for Division-free Linear System Solving. Comput. J. 39(8): 713-722 (1996) - [c6]Shietung Peng, Stanislav Sedukhin, Igor S. Sedukhin:
Parallel Algorithm And Architecture For Two-Step Division-Free Gaussian Elimination. ASAP 1996: 183-192 - [c5]Stanislav Sedukhin, Igor S. Sedukhin:
Parallel Rendering with the Network Linda System. PDPTA 1996: 879-889 - 1995
- [c4]Stanislav G. Sedukhin:
An Algorithm and Array Processor for Solving the Systems of Linear Equations. PDPTA 1995: 307-316 - 1994
- [c3]Stanislav Sedukhin, Igor S. Sedukhin:
Systematic Approach and Software Tool for Systolic Design. CONPAR 1994: 172-183 - [c2]Stanislav G. Sedukhin:
A new systolic architecture for pipeline prime factor DFT-algorithm. Great Lakes Symposium on VLSI 1994: 40-45 - 1990
- [c1]Stanislav Sedukhin:
Systolic Array Architecture for Two-Dimensional Discrete Fourier Transform. CONPAR 1990: 682-691
Coauthor Index
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