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ORCIDAbhijit R. Asati
Person information
- affiliation: Birla Institute Of Technology and Science (BITS), Pilani, India
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2020 – today
- 2022
[j15]Vineet Kumar
, Abhijit R. Asati, Anu Gupta:
Dedicated hardware architecture for localizing iris in VW images. J. King Saud Univ. Comput. Inf. Sci. 34(7): 4568-4578 (2022)- [j14]Prateek Sikka, Abhijit R. Asati, Chandra Shekhar:
Area, Speed and Power Optimized Implementation of a Band-Pass FIR Filter Using High-Level Synthesis. Wirel. Pers. Commun. 127(3): 1869-1878 (2022) - 2021
- [j13]Prateek Sikka, Abhijit R. Asati, Chandra Shekhar:
High-speed and area-efficient Sobel edge detector on field-programmable gate array for artificial intelligence and machine learning applications. Comput. Intell. 37(3): 1056-1067 (2021) - [j12]Prateek Sikka, Abhijit R. Asati, Chandra Shekhar:
Power- and Area-Optimized High-Level Synthesis Implementation of a Digital Down Converter for Software-Defined Radio Applications. Circuits Syst. Signal Process. 40(6): 2883-2894 (2021) - [j11]Prateek Sikka, Abhijit R. Asati, Chandra Shekhar:
Real time FPGA implementation of a high speed and area optimized Harris corner detection algorithm. Microprocess. Microsystems 80: 103514 (2021) - 2020
- [j10]Prateek Sikka, Abhijit R. Asati, Chandra Shekhar:
High-Level synthesis assisted design and verification framework for automotive radar processors. Microprocess. Microsystems 78: 103259 (2020) - [j9]Prateek Sikka, Abhijit R. Asati, Chandra Shekhar:
Speed optimal FPGA implementation of the encryption algorithms for telecom applications. Microprocess. Microsystems 79: 103324 (2020)
2010 – 2019
- 2018
- [j8]Vineet Kumar, Abhijit R. Asati, Anu Gupta:
Memory-efficient architecture of circle Hough transform and its FPGA implementation for iris localisation. IET Image Process. 12(10): 1753-1761 (2018) - [j7]Vineet Kumar, Abhijit R. Asati, Anu Gupta:
Hardware Accelerators for Iris Localization. J. Signal Process. Syst. 90(4): 655-671 (2018) - 2017
- [j6]Vineet Kumar, Abhijit R. Asati, Anu Gupta:
Low-latency median filter core for hardware implementation of 5 × 5 median filtering. IET Image Process. 11(10): 927-934 (2017) - [j5]Ashish Mishra, Mohit Agarwal, Abhijit Rameshwar Asati, Kota Solomon Raju:
Using graph isomorphism for mapping of data flow applications on reconfigurable computing systems. Microprocess. Microsystems 51: 343-355 (2017) - 2016
- [j4]Vineet Kumar, Abhijit R. Asati, Anu Gupta:
A Novel Edge-Map Creation Approach for Highly Accurate Pupil Localization in Unconstrained Infrared Iris Images. J. Electr. Comput. Eng. 2016: 4709876:1-4709876:10 (2016) - 2015
- [j3]Priya Gupta, Anu Gupta, Abhijit R. Asati:
Leakage Immune Modified Pass Transistor Based 8T SRAM Cell in Subthreshold Region. Int. J. Reconfigurable Comput. 2015: 749816:1-749816:10 (2015) - [c5]Vineet Kumar, Abhijit R. Asati, Anu Gupta:
An Iris localization method for noisy infrared iris images. ICSIPA 2015: 208-213 - 2014
- [c4]Ankur Kumar, Abhijit R. Asati:
Iris based biometric identification system. ICAILP 2014: 260-265 - 2012
- [c3]Deepak Bharti, Abhijit R. Asati:
Design of a Static Current Simulator Using Device Matrix Approach. ISED 2012: 193-197 - 2010
- [j2]Subhendu Kumar Sahoo, Anu Gupta, Abhijit R. Asati, Chandra Shekhar:
A Novel Redundant Binary Number to Natural Binary Number Converter. J. Signal Process. Syst. 59(3): 297-307 (2010)
2000 – 2009
- 2009
- [j1]Subhendu Kumar Sahoo, Chandra Shekhar, Sudeepti Kodali, Abhijit R. Asati, Anu Gupta:
Dual channel addition based FFT processor architecture for signal and image processing. Int. J. High Perform. Syst. Archit. 2(1): 35-45 (2009) - [c2]Abhijit R. Asati, Subhendu Kumar Sahoo, Chandra Shekhar:
Selection of Optimum Device Size and Trans-Conductance Ratio for High Speed Digital CMOS Inverter Design for a Given Fanout Load. ICETET 2009: 121-124 - 2008
- [c1]Abhijit R. Asati, Chandrashekhar:
An improved high speed fully pipelined 500 MHz 8×8 baugh wooley multiplier design using 0.6 μm CMOS TSPC logic design style. ICIIS 2008: 1-6
Coauthor Index
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