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ORCIDRuben Gran Tejero
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2020 – today
- 2024
[j21]Yamilka Toca-Díaz, Reynier Hernández Palacios, Ruben Gran Tejero, Alejandro Valero
:
Flip-and-Patch: A fault-tolerant technique for on-chip memories of CNN accelerators at low supply voltage. Microprocess. Microsystems 106: 105023 (2024)- 2023
- [c13]Yamilka Toca-Díaz, Nicolás Landeros Muñoz, Ruben Gran Tejero, Alejandro Valero:
On Fault-Tolerant Microarchitectural Techniques for Voltage Underscaling in On-Chip Memories of CNN Accelerators. DSD 2023: 138-145 - 2022
- [j20]Maria Angélica Dávila-Guzmán, Lester Kalms, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia, Diana Göhringer:
A cross-platform OpenVX library for FPGA accelerators. J. Syst. Archit. 123: 102372 (2022) - [j19]Andrés Rodríguez, Angeles G. Navarro, Kris Nikov, José L. Núñez-Yáñez, Ruben Gran, Darío Suárez Gracia, Rafael Asenjo:
Lightweight asynchronous scheduling in heterogeneous reconfigurable systems. J. Syst. Archit. 124: 102398 (2022) - [j18]Nicolás Landeros Muñoz, Alejandro Valero, Ruben Gran Tejero, Davide Zoni:
Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators. J. Syst. Archit. 128: 102553 (2022) - [c12]Darío Suárez Gracia, Alejandro Valero, Ruben Gran Tejero, María Villarroya-Gaudó, Víctor Viñals:
peRISCVcope: A Tiny Teaching-Oriented RISC-V Interpreter. DCIS 2022: 1-6 - 2021
- [j17]Alejandro Valero, Ruben Gran Tejero, Darío Suárez Gracia, Emanuel A. Georgescu, Joaquín Ezpeleta, Pedro Álvarez, Adolfo Muñoz, Luis M. Ramos, Pablo Ibáñez:
A learning experience toward the understanding of abstraction-level interactions in parallel applications. J. Parallel Distributed Comput. 156: 38-52 (2021) - [j16]Juan Segarra, Ruben Gran Tejero, Víctor Viñals:
A generic framework to integrate data caches in the WCET analysis of real-time systems. J. Syst. Archit. 120: 102304 (2021) - [j15]Maria Angélica Dávila-Guzmán, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia:
Analytical Model for Memory-Centric High Level Synthesis-Generated Applications. IEEE Trans. Computers 70(12): 2056-2069 (2021) - [c11]Maria Angélica Dávila-Guzmán, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia, Lester Kalms, Diana Göhringer:
A Cross-Platform OpenVX Library for FPGA Accelerators. PDP 2021: 75-83 - [i3]Yamilka Toca-Díaz, Alejandro Valero, Ruben Gran Tejero, Darío Suárez Gracia:
RRCD: Redirección de Registros Basada en Compresión de Datos para Tolerar FallosPermanentes en una GPU. CoRR abs/2105.03859 (2021) - 2020
- [j14]Alejandro Valero, Darío Suárez Gracia, Ruben Gran Tejero:
DC-Patch: A Microarchitectural Fault Patching Technique for GPU Register Files. IEEE Access 8: 173276-173288 (2020) - [j13]Juan Segarra, Jordi Cortadella, Ruben Gran Tejero, Víctor Viñals Yúfera:
Automatic Safe Data Reuse Detection for the WCET Analysis of Systems With Data Caches. IEEE Access 8: 192379-192392 (2020) - [j12]Andrés Rodríguez, Angeles G. Navarro, Rafael Asenjo, Francisco Corbera, Ruben Gran, Darío Suárez Gracia, José L. Núñez-Yáñez:
Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform. J. Supercomput. 76(6): 4645-4665 (2020) - [c10]Maria Angelica Davila Guzman, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia:
An Analytical Model of Memory-Bound Applications Compiled with High Level Synthesis. FCCM 2020: 218 - [i2]Maria Angelica Davila Guzman, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia:
Analytical Model of Memory-Bound Applications Compiled with High Level Synthesis. CoRR abs/2003.13054 (2020)
2010 – 2019
- 2019
- [j11]Andrés Rodríguez, Angeles G. Navarro, Rafael Asenjo, Francisco Corbera, Ruben Gran Tejero, Darío Suárez Gracia, José L. Núñez-Yáñez:
Exploring heterogeneous scheduling for edge computing with CPU and FPGA MPSoCs. J. Syst. Archit. 98: 27-40 (2019) - [j10]Maria Angelica Davila Guzman, Raúl Nozal, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia, José Luis Bosque:
Cooperative CPU, GPU, and FPGA heterogeneous execution with EngineCL. J. Supercomput. 75(3): 1732-1746 (2019) - [j9]José L. Núñez-Yáñez, Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Darío Suárez Gracia, Ruben Gran:
Simultaneous multiprocessing in a software-defined heterogeneous FPGA. J. Supercomput. 75(8): 4078-4095 (2019) - [j8]José L. Núñez-Yáñez, Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Darío Suárez Gracia, Ruben Gran:
Correction to: Simultaneous multiprocessing in a software-defined heterogeneous FPGA. J. Supercomput. 75(8): 4096-4097 (2019) - [c9]Alejandro Valero, Darío Suárez Gracia, Ruben Gran Tejero, Luis M. Ramos, Agustín Navarro-Torres, Adolfo Muñoz, Joaquín Ezpeleta, José Luis Briz, Ana C. Murillo, Eduardo Montijano, Javier Resano, María Villarroya-Gaudó, Jesús Alastruey-Benedé, Enrique F. Torres, Pedro Álvarez, Pablo Ibáñez, Víctor Viñals:
Exposing Abstraction-Level Interactions with a Parallel Ray Tracer. WCAE@ISCA 2019: 5:1-5:8 - 2018
- [c8]Maria Angelica Davila Guzman, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia:
Towards the Inclusion of FPGAs on Commodity Heterogeneous Systems. HPCS 2018: 554-556 - [i1]José L. Núñez-Yáñez, Mohammad Hosseinabady, Moslem Amiri, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Ruben Gran Tejero, Darío Suárez Gracia:
Parallelizing Workload Execution in Embedded and High-Performance Heterogeneous Systems. CoRR abs/1802.03316 (2018) - 2017
- [c7]José L. Núñez-Yáñez, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Ruben Gran Tejero, Darío Suárez Gracia:
Simultaneous Multiprocessing on a FPGA+CPU Heterogeneous System-On-Chip. PARCO 2017: 677-686 - 2016
- [j7]Antonio Vilches, Angeles G. Navarro, Rafael Asenjo, Francisco Corbera, Ruben Gran, María Jesús Garzarán:
Mapping Streaming Applications on Commodity Multi-CPU and GPU On-Chip Processors. IEEE Trans. Parallel Distributed Syst. 27(4): 1099-1115 (2016) - [j6]Juan Antonio Clemente, Ruben Gran, Abel Chocano, Carlos del Prado, Javier Resano:
Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 530-543 (2016) - 2015
- [j5]Ruben Gran, Juan Segarra, A. Pedro-Zapater, Luis C. Aparicio, Víctor Viñals, Clemente Rodríguez:
A predictable hardware to exploit temporal reuse in real-time and embedded systems. J. Syst. Archit. 61(5-6): 227-238 (2015) - [j4]Javier Olivito, Ruben Gran, Javier Resano, Carlos González, Enrique F. Torres:
Performance and energy efficiency analysis of a Reversi player for FPGAs and General Purpose Processors. Microprocess. Microsystems 39(2): 64-73 (2015) - [j3]Juan Segarra, Clemente Rodríguez, Ruben Gran, Luis C. Aparicio, Víctor Viñals:
ACDC: Small, Predictable and High-Performance Data Cache. ACM Trans. Embed. Comput. Syst. 14(2): 38:1-38:26 (2015) - [c6]Antonio Vilches, Rafael Asenjo, Angeles G. Navarro, Francisco Corbera, Ruben Gran Tejero, María Jesús Garzarán:
Adaptive Partitioning for Irregular Applications on Heterogeneous CPU-GPU Chips. ICCS 2015: 140-149 - 2014
- [c5]Swapnil Ghike, Ruben Gran, María Jesús Garzarán, David A. Padua:
Directive-Based Compilers for GPUs. LCPC 2014: 19-35 - [c4]Ruben Gran, August Shi, Ehsan Totoni, María Jesús Garzarán:
Evaluation of a Feature Tracking Vision Application on a Heterogeneous Chip. SBAC-PAD 2014: 246-253 - 2013
- [j2]Ruben Gran Tejero, Juan Segarra, Clemente Rodríguez, Luis C. Aparicio, Víctor Viñals:
Optimizing a combined WCET-WCEC problem in instruction fetching for real-time systems. J. Syst. Archit. 59(9): 667-678 (2013) - 2012
- [j1]Jorge Albericio, Ruben Gran Tejero, Pablo Ibáñez, Víctor Viñals, José María Llabería:
ABS: A low-cost adaptive controller for prefetching in a banked shared last-level cache. ACM Trans. Archit. Code Optim. 8(4): 19:1-19:20 (2012) - [c3]Juan Segarra, Clemente Rodríguez, Ruben Gran Tejero, Luis C. Aparicio, Víctor Viñals:
A Small and Effective Data Cache for Real-Time Multitasking Systems. IEEE Real-Time and Embedded Technology and Applications Symposium 2012: 45-54
2000 – 2009
- 2009
- [c2]Ruben Gran Tejero, Enric Morancho, Àngel Olivé, José María Llabería:
On reducing misspeculations in a pipelined scheduler. IPDPS 2009: 1-12 - 2006
- [c1]Ruben Gran Tejero, Enric Morancho, Àngel Olivé, José María Llabería:
An Enhancement for a Scheduling Logic Pipelined over two Cycles . ICCD 2006: 203-209
Coauthor Index
aka: Maria Angélica Dávila-Guzmán
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