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2020 – today
- 2024
[j36]Ming-Hwa Sheu
, En-Chi Yang, Szu-Ting Wang, Wen-Ho Juang, Shin-Chi Lai:
High Precision, Low Complexity, and Fast Calculation Based on Hybrid Recursive DFT and FFT Algorithms for Electrochemical Impedance Spectroscopy System. IEEE Trans. Instrum. Meas. 73: 1-14 (2024)- 2023
- [j35]Ming-Hwa Sheu, S. M. Salahuddin Morsalin, Chung-Chian Hsu, Shin-Chi Lai, Szu-Hong Wang, Chuan-Yu Chang:
Improvement of Human Pose Estimation and Processing With the Intensive Feature Consistency Network. IEEE Access 11: 28045-28059 (2023) - [j34]Wen-Ho Juang, En-Chi Yang, Szu-Ting Wang, Ming-Hwa Sheu, How-Chiun Wu, Shin-Chi Lai:
Portable RDFT-Based EIS System Design With a Low-Complexity Impedance Calculation. IEEE Trans. Instrum. Meas. 72: 1-15 (2023) - [c69]Shih-Chang Hsia, Szu-Hong Wang, Ming-Hwa Sheu, Wei-Chien Yuan:
A Low-Complexity Convolution Network for Upscale Super-Resolution Image. ICKII 2023: 177-180 - [c68]Ming-Hwa Sheu, S. M. Salahuddin Morsalin, Yi-Wen Chang, Szu-Hong Wang, Chung-Chian Hsu, Shin-Chi Lai:
Unique Feature Extraction and Consistency Network for Skeleton Body Keypoints Configuration and Enhancement. ICKII 2023: 667-670 - [c67]Yen-Ching Chang, Szu-Ting Wang, Ying-Hsiu Hung, Yao-Feng Liang, Ming-Hwa Sheu, Shin-Chi Lai:
Heart Valve Disease Recognition Using Phonocardiogram Signal Based on A Lightweight Convolution Neural Network. ISOCC 2023: 103-105 - [c66]En-Chi Yang, Suz-Ting Wang, Kusn-Lin Liu, Wen-Ho Juang, Ming-Hwa Sheu, How-Chiun Wu, Shin-Chi Lai:
Fast Measurement of Impedance Calculation for Electrochemical Impedance Spectroscopy. ISOCC 2023: 177-178 - [c65]Ying-Hsiu Hung, Yen-Ching Chang, Suz-Ting Wang, Jeng-Dao Lee, Wen-Ho Juang, Ming-Hwa Sheu, Shin-Chi Lai:
Convolutional Neural Network-based Keyword Classification for Mixer Control. ISOCC 2023: 181-182 - 2022
- [j33]Ming-Hwa Sheu, S. M. Salahuddin Morsalin, Szu-Hong Wang, Lin-Keng Wei, Shih-Chang Hsia, Chuan-Yu Chang:
FHI-Unet: Faster Heterogeneous Images Semantic Segmentation Design and Edge AI Implementation for Visible and Thermal Images Processing. IEEE Access 10: 18596-18607 (2022) - [j32]Yu-Syuan Jhang, Szu-Ting Wang, Ming-Hwa Sheu, Szu-Hong Wang, Shin-Chi Lai:
Integration Design of Portable ECG Signal Acquisition With Deep-Learning Based Electrode Motion Artifact Removal on an Embedded System. IEEE Access 10: 57555-57564 (2022) - [j31]Ming-Hwa Sheu, S. M. Salahuddin Morsalin, Szu-Hong Wang, Yu-Teng Shen, Shih-Chang Hsia, Chuan-Yu Chang:
FIBS-Unet: Feature Integration and Block Smoothing Network for Single Image Dehazing. IEEE Access 10: 71764-71776 (2022) - [j30]Shin-Chi Lai, Ying-Hsiu Hung, Yi-Chang Zhu, Szu-Ting Wang, Qi-Xian Huang, Ming-Hwa Sheu, Wen-Ho Juang:
Hardware Accelerator Design of DCT Algorithm With Unique-Group Cosine Coefficients for Mel-Scale Frequency Cepstral Coefficients. IEEE Access 10: 79681-79688 (2022) - [j29]Ming-Hwa Sheu, Yu-Syuan Jhang, Yen-Ching Chang, Szu-Ting Wang, Chuan-Yu Chang, Shin-Chi Lai:
Lightweight Denoising Autoencoder Design for Noise Removal in Electrocardiography. IEEE Access 10: 98104-98116 (2022) - 2021
- [j28]Shih-Chang Hsia, Ming-Hwa Sheu, Jhih-Jian Jhou:
Fast-transient high-voltage buck-boost DC-DC conversion with low overshoot. Microelectron. J. 110: 105016 (2021) - [j27]Ming-Hwa Sheu, Chang-Ming Tsai, Ming-Yan Tsai, Shih-Chang Hsia, S. M. Salahuddin Morsalin, Jin-Fa Lin:
A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications. Sensors 21(19): 6591 (2021) - [j26]Ming-Hwa Sheu, S. M. Salahuddin Morsalin, Jia-Xiang Zheng, Shih-Chang Hsia, Cheng-Jian Lin, Chuan-Yu Chang:
FGSC: Fuzzy Guided Scale Choice SSD Model for Edge AI Design on Real-Time Vehicle Detection and Class Counting. Sensors 21(21): 7399 (2021) - [c64]Bo-Wei Chen, Yu-Syuan Jhang, Hao-Ting Pai, Szu-Hong Wang, Ming-Hwa Sheu, Tzu-Hsiung Chen:
AIoT-based Audio Recognition System for Smart Home Applications. ICCE-TW 2021: 1-2 - [c63]Guan-Zhou Lin, Hoang Minh Nguyen, Chi-Chia Sun, Po-Yu Kuo, Ming-Hwa Sheu:
A Novel Bird Detection and Identification based on DPU processor on PYNQ FPGA. ICCE-TW 2021: 1-2 - [c62]En-Chi Yang, Ming Jie Lee, Wen-Ho Juang, Ming-Hwa Sheu, Shin-Chi Lai:
Font-End Integrated Circuit Design for Plant Physiological Sensing. ICCE-TW 2021: 1-2 - [c61]Wei-Yu Zhu, Wing-Kwong Wong, S. M. Salahuddin Morsalin, Szu-Hong Wang, Ming-Hwa Sheu:
Software and Hardware Integration System Design with Fruit Identification for Smart Electronic Scale Applications. ICCE-TW 2021: 1-2 - [c60]Shih-Chang Hsia, Szu-Hong Wang, Ho-Cheng Tsai, Ming-Hwa Sheu:
Real-time Stereo Television Broadcasting System. ICCE 2021: 1-5 - 2020
- [j25]Shih-Chang Hsia, Ming-Hwa Sheu, Jyun-Jia Ciou:
Cost-Effective LED Dimming Driver With Single Chip Design for Smart Lighting System. IEEE Access 8: 141025-141032 (2020) - [c59]Yu-Sheng Yang, Che-Wei Chen, Ming-Hwa Sheu, Szu-Hong Wang, Tzu-Hsiung Chen:
Real-Time Lighter Sound Recognition System for IoT Applications. ICCE-TW 2020: 1-2
2010 – 2019
- 2019
- [j24]Chi-Chia Sun, Ming-Hwa Sheu, Jui-Yang Chi, Yan-Kai Huang:
A Fast Non-Overlapping Multi-Camera People Re-Identification Algorithm and Tracking Based on Visual Channel Model. IEICE Trans. Inf. Syst. 102-D(7): 1342-1348 (2019) - [j23]Po-Yu Kuo, Chia-Hsin Hsieh, Jin-Fa Lin, Ming-Hwa Sheu, Yi-Ting Hung:
Low Complexity and Low Power Sense-Amplifier Based Flip-Flop Design. IEICE Trans. Electron. 102-C(11): 833-838 (2019) - [c58]Tsung-Han Tsai, Yuan-Chen Ho, Ming-Hwa Sheu:
Implementation of FPGA-based Accelerator for Deep Neural Networks. DDECS 2019: 1-4 - [c57]Cheng-Jie Yang, Ming-Jie Li, Chen-Yueh Liu, Ming-Hwa Sheu, Chi-Chia Sun:
Low-Power Counter-Based Delay Line Design For DPWM. ICCE-TW 2019: 1-2 - [c56]Shih-Chang Hsia, Ming-Hwa Sheu, Cheng Hung Hsiao:
The Image Shape Recovery on Communication Data Lost Damage. ICUFN 2019: 206-210 - 2018
- [c55]Ming-Yan Tsai, Po-Yu Kuo, Jin-Fa Lin, Ming-Hwa Sheu:
An Ultra-low-power True Single-phase Clocking Flip-flop with Improved Hold time Variation using Logic Structure Reduction Scheme. ISCAS 2018: 1-4 - 2017
- [j22]Jin-Fa Lin, Ming-Hwa Sheu, Yin-Tsung Hwang, Chen-Syuan Wong, Ming-Yan Tsai:
Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes. IEEE Trans. Very Large Scale Integr. Syst. 25(11): 3033-3044 (2017) - [c54]Siang-Min Siao, Ming-Hwa Sheu, Shao-Yu Wang:
High-performance reverse converter design for the new four-moduli Set {22n, 2n+1, 2n/2+1, 2n/2-1}. DSC 2017: 1-2 - [c53]Chi-Chia Sun, Ming-Hwa Sheu, Yu-Cheng Syu:
A new fall detection algorithm based on depth information using RGB-D camera. ISPACS 2017: 413-416 - 2016
- [j21]Ming-Hwa Sheu, Siang-Min Siao, Yin-Tsung Hwang, Chi-Chia Sun, You-Ping Lin:
New adaptable three-moduli set {2n+k, 2n - 1, 2n-1 - 1} for residue number system-based finite impulse response implementation. IEICE Electron. Express 13(11): 20160090 (2016) - [c52]Kai Xiang Yang, Ming-Hwa Sheu:
Edge-based moving object tracking algorithm for an embedded system. APCCAS 2016: 153-155 - [c51]Ming-Hwa Sheu, Li Hung Chang, Shih-Chang Hsia, Chi-Chia Sun:
Intelligent system design for variable color temperature LED street light. ICCE-TW 2016: 1-2 - [c50]Wen-Kai Tsai, Jian-Hui Chen, Ming-Hwa Sheu, Chi-Chia Sun:
Object detection using adaptive block-based background model. ICCE-TW 2016: 1-2 - [c49]Chi-Chia Sun, Heng-Chi Lai, Ming-Hwa Sheu, Yi-Hsing Huang:
Single image fog removal algorithm based on an improved dark channel prior method. ISPACS 2016: 1-4 - 2015
- [c48]Yi-Hua Wang, Ming-Hwa Sheu, Chi-Chia Sun:
Efficient object motion detection based on RGB-D image. ICCE-TW 2015: 438-439 - [c47]Ming-Hwa Sheu, Shyue-Wen Yang, Tzu-Hsiung Chen:
Extendable multi-pixel object labeling for digital image. ICCE-TW 2015: 440-441 - [c46]Chi-Chia Sun, Heng-Chi Lai, Sin-Kun Lin, Ming-Hwa Sheu, Mladen Berekovic:
High efficient hardware allocation framework of arbitrary inverse transform coding blocks in H.265. ISPACS 2015: 36-39 - 2014
- [c45]Chi-Chia Sun, Cheng Chih Wang, Ming-Hwa Sheu:
Ultra Low Power Circuit Design Based on Adiabatic Logic. IIH-MSP 2014: 317-320 - [c44]Yin-Tsung Hwang, Bing Cheng Tsai, Yu-Ting Pai, Ming-Hwa Sheu:
Feature Points Based Video Object Tracking for Dynamic Scenes and Its FPGA System Prototyping. IIH-MSP 2014: 325-328 - [c43]Wen-Kai Tsai, Chang Jie Lai, Ming-Hwa Sheu, Tsu Hsiung Chen:
High Dynamic Range Image Based on Block-Based Edge Strength for Embedded System Design. IIH-MSP 2014: 329-332 - 2013
- [j20]Ming-Hwa Sheu, Yuan-Ching Kuo, Su-Hon Lin, Siang-Min Siao:
Efficient Reverse Converter Design for New Adaptable Four-Moduli Set {2n + k, 2n + 1, 2n - 1, 22n + 1}. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(7): 1571-1578 (2013) - [c42]Chen-Hong Yuan, Jeng-Shyang Pan, Ming-Hwa Sheu, Tzu-Hsiung Chen:
Fast Image Blending and Deghosting for Panoramic Video. IIH-MSP 2013: 104-107 - [c41]Ho-En Liao, Guan-Yu Lin, Ming-Hwa Sheu, Siang-Min Siao, Sin-Siang Wan:
A Computation Efficiency AND-CFAR for FMCW Radar Receiver. IIH-MSP 2013: 108-112 - 2012
- [j19]Wen-Kai Tsai, Ming-Hwa Sheu, Chung-Chi Lin:
Block-Based Major Color Method for Foreground Object Detection on Embedded SoC Platforms. IEEE Embed. Syst. Lett. 4(2): 49-52 (2012) - [j18]Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu:
Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme. IEEE Trans. Very Large Scale Integr. Syst. 20(2): 361-366 (2012) - [c40]Wen-Kai Tsai, Ming-Hwa Sheu, Chung-Chi Lin:
Region-Based Background Subtraction for Complex Sense on Embedded Platforms. IIH-MSP 2012: 351-354 - [c39]Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu:
Low power 10-transistor full adder design based on degenerate pass transistor logic. ISCAS 2012: 496-499 - [c38]Shyue-Wen Yang, Ming-Hwa Sheu, Wen-Kai Tsai:
Fast image moving object segmentation based on block texture for embedded system implementation. ISPACS 2012: 649-652 - [c37]Wen-Kai Tsai, Ming-Hwa Sheu, Chung-Chi Lin, Ho-En Liao:
A robust background modeling and foreground object detection using color component analysis. SMC 2012: 263-267 - [c36]Chung-Chi Lin, Wen-Kai Tsai, Ming-Hwa Sheu:
A hybrid pixel-based background model for image foreground object detection in complex sence. TSP 2012: 720-724 - 2011
- [c35]Jian-Hui Chen, Wen-Kai Tsai, Ming-Hwa Sheu, Kai-Min Lin, Ho-En Liao:
Efficient Color-Ingredient Particle Filter for Video Object Tracking. IBICA 2011: 49-52 - [c34]Yuan-Ching Kuo, Ming-Hwa Sheu, Siang-Min Siao, Cheng-Yi Huang, Tzu-Hsiung Chen:
New Reverse Converter Design of Moduli Set {2n, 2n+1-1, 2n-1}. IBICA 2011: 253-256 - 2010
- [j17]Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu:
A Low Complexity Low Power Signal Transition Detector Design for Self-Timed Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(4): 843-845 (2010) - [j16]Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu:
Low Power Pulse Generator Design Using Hybrid Logic. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(6): 1266-1268 (2010) - [j15]Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu:
A Low Complexity Dual-Mode Pulse-Triggered Flip-Flop Design Based on Unified AND/XNOR Logic. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2755-2757 (2010) - [j14]Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw, Zeng-Chuan Wu, Wen-Kai Tsai:
An Efficient Architecture of Extended Linear Interpolation for Image Processing. J. Inf. Sci. Eng. 26(2): 631-648 (2010) - [j13]Chung-Chi Lin, Ming-Hwa Sheu, Chishyan Liaw, Huann-Keng Chiang:
Fast First-Order Polynomials Convolution Interpolation for Real-Time Digital Image Reconstruction. IEEE Trans. Circuits Syst. Video Technol. 20(9): 1260-1264 (2010) - [c33]Ming-Hwa Sheu, Shyue-Wen Yang, Wen-Sheng Huang, Siang-Min Siao:
FPGA implementation for image object detection system on NoCs. APCCAS 2010: 560-563 - [c32]Ming-Hwa Sheu, Wen-Kai Tsai, Chuang-Chun Hu, Chun-Heng Tsao:
Fast Texture-Based Object Tracking Algorithm on Embedded Platform. FCST 2010: 511-514 - [c31]Wen-Kai Tsai, Ming-Hwa Sheu, Chung-Chi Lin:
Efficient Multi-Layer Background Model on Complex Environment for Foreground Object Detection. IIH-MSP 2010: 292-295
2000 – 2009
- 2009
- [c30]Shyue-Wen Yang, Ming-Hwa Sheu, Jun-Jie Lin, Chuang-Chun Hu, Tzu-Hsiung Chen, Shau-Yin Tseng:
Parallel 3-Pixel Labeling Method and its Hardware Architecture Design. IAS 2009: 185-188 - [c29]Wen-Kai Tsai, Ming-Hwa Sheu, Ching-Lung Su, Jun-Jie Lin, Shau-Yin Tseng:
Image Object Detection and Tracking Implementation for Outdoor Scenes on an Embedded Soc Platform. IIH-MSP 2009: 386-389 - [c28]Yuan-Ching Kuo, Su-Hon Lin, Ming-Hwa Sheu, Jia-You Wu, Peng-Siang Wang:
Efficient VLSI Design of a Reverse RNS Converter for New Flexible 4-Moduli Set (2p+k, 2p+1, 2p-1, 22p+1). ISCAS 2009: 437-440 - 2008
- [j12]Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw, Zeng-Chuan Wu:
An efficient convolution interpolation kernel for digital image scaling. IEICE Electron. Express 5(20): 860-864 (2008) - [j11]Su-Hon Lin, Ming-Hwa Sheu:
Area-Time Efficient Modulo 2n - 1 Adder Design Using Hybrid Carry Selection. IEICE Trans. Inf. Syst. 91-D(2): 361-362 (2008) - [j10]Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu:
Low Complexity Dual-Mode Pulse Generator Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(7): 1812-1815 (2008) - [j9]Su-Hon Lin, Ming-Hwa Sheu, Chao-Hsiang Wang:
Efficient VLSI Design of Residue-to-Binary Converter for the Moduli Set (2n, 2n+1 - 1, 2n - 1). IEICE Trans. Inf. Syst. 91-D(7): 2058-2060 (2008) - [j8]Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw:
High-performance very large scale integration architecture design for various-ratio image scaling. J. Electronic Imaging 17(4): 043010 (2008) - [j7]Su-Hon Lin, Ming-Hwa Sheu:
VLSI Design of Diminished-One Modulo 2n+1 Adder Using Circular Carry Selection. IEEE Trans. Circuits Syst. II Express Briefs 55-II(9): 897-901 (2008) - [c27]Su-Hon Lin, Ming-Hwa Sheu, Chao-Hsiang Wang, Yuan-Ching Kuo:
Area-time-power efficient VLSI design for residue-to-binary converter based on moduli set (2n, 2n+1-1, 2n-1). APCCAS 2008: 168-171 - [c26]Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Wen-Kai Tsai, Zeng-Chuan Wu:
Real-time FPGA architecture of extended linear convolution for digital image scaling. FPT 2008: 381-384 - [c25]Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Zeng-Chuan Wu, Jia-Yi Tu, Chia-Hung Chen:
A Low-cost VLSI Design of Extended Linear Interpolation for Real Time Digital Image Processing. ICESS 2008: 196-202 - [c24]Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw, Zeng-Chuan Wu:
The efficient VLSI design of BI-CUBIC convolution interpolation for digital image processing. ISCAS 2008: 480-483 - 2007
- [j6]Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chih-Jen Wei, Chishyan Liaw:
A High-Performance Architecture of Motion Adaptive De-interlacing with Reliable Interfield Information. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(11): 2575-2583 (2007) - [j5]Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, Cheng-Che Ho:
A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(5): 1050-1059 (2007) - [c23]Chung-Chi Lin, Zeng-Chuan Wu, Wen-Kai Tsai, Ming-Hwa Sheu, Huann-Keng Chiang:
The VLSI Design of Winscale for Digital Image Scaling. IIH-MSP 2007: 511-514 - [c22]Shyue-Wen Yang, Ming-Hwa Sheu, Chun-Kai Yeh, Chih-Yuen Wen, Chih-Chieh Lin, Wen-Kai Tsai:
Fast Fair Crossbar Scheduler for On-chip Router. ISCAS 2007: 385-388 - [c21]Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu, Chia-Jen Sheu:
Low Power Multipliers Using Enhenced Row Bypassing Schemes. SiPS 2007: 136-141 - [c20]Su-Hon Lin, Ming-Hwa Sheu, Kuang-Hui Wang, Jun-Jie Zhu, Si-Ying Chen:
Efficient VLSI Design of Modulo 2n-1 Adder Using Hybrid Carry Selection. SiPS 2007: 142-145 - 2006
- [c19]Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu, Chia-Jen Sheu:
Low Power Multiplier Designs Based on Improved Column Bypassing Schemes. APCCAS 2006: 594-597 - [c18]Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chih-Jen Wei:
The VLSI Design of Motion Adaptive De-interlacing with Horizontal and Vertical Motions Detection. APCCAS 2006: 1587-1590 - [c17]Su-Hon Lin, Ming-Hwa Sheu, Jing-Shiun Lin, Wen-Tsai Sheu:
Efficient VLSI Design for RNS Reverse Converter Based on New Moduli Set (2n-1, 2n+1, 22n+1). APCCAS 2006: 2020-2023 - [c16]Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw, Ming-Che Chen:
Film-to-Video Conversion with Scene Cut Detection. ICICIC (1) 2006: 285-289 - [c15]Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, Cheng-Che Ho:
A high speed and energy efficient full adder design using complementary & level restoring carry logic. ISCAS 2006 - [c14]Chung-Chi Lin, Chih-Jen Wei, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw:
The VLSI design of de-interlacing with scene change detection. ISCAS 2006 - [c13]Yin-Tsung Hwang, Jiun-Yan Chen, Ming-Hwa Sheu:
Automatic Generation of Programmable Parallel CRC & Scrambler Designs. SiPS 2006: 286-291 - 2005
- [c12]Shyue-Wen Yang, Ming-Hwa Sheu, Hsien-Huang P. Wu, Hung-En Chien, Ping-Kuo Weng, Ying-Yih Wu:
VLSI architecture design for a fast parallel label assignment in binary image. ISCAS (3) 2005: 2393-2396 - [c11]Hsien-Huang P. Wu, Ming-Hwa Sheu, Tung-Yu Yang:
Directional interpolation for field-sequential stereoscopic video. ISCAS (3) 2005: 2879-2882 - [c10]Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw:
Motion Adaptive De-interlacing with Horizontal and Vertical Motions Detection. PCM (1) 2005: 291-302 - 2004
- [j4]Ming-Hwa Sheu, Su-Hon Lin, Chichyang Chen, Shyue-Wen Yang:
An efficient VLSI design for a residue to binary converter for general balance moduli (2n-3, 2n+1, 2n-1, 2n+3). IEEE Trans. Circuits Syst. II Express Briefs 51-II(3): 152-155 (2004) - 2003
- [c9]Chichyang Chen, Rui-Lin Chen, Ming-Hwa Sheu:
A Fast Additive Normalization Method for Exponential Computation. DSD 2003: 286-293 - 2002
- [j3]Ming-Hwa Sheu, Su-Hon Lin:
Fast compensative design approach for the approximate squaring function. IEEE J. Solid State Circuits 37(1): 95-97 (2002) - [c8]Ming-Hwa Sheu, Su-Hon Lin:
Fast design approach for implementing the approximate squaring function. APCCAS (2) 2002: 25-29 - 2001
- [j2]Ming-Der Shieh, Ming-Hwa Sheu, Chung-Ho Chen, Hsin-Fu Lo:
A Systematic Approach for Parallel CRC Computations. J. Inf. Sci. Eng. 17(3): 445-461 (2001) - [c7]Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu:
VLSI architecture of extended in-place path metric update for Viterbi decoders. ISCAS (4) 2001: 206-209 - [c6]Ming-Hwa Sheu, Ho-En Liao, Shih Tsung Kan, Ming-Der Shieh:
A novel adaptive algorithm and VLSI design for frequency detection in noisy environment based on adaptive IIR filter. ISCAS (4) 2001: 446-449 - 2000
- [c5]Ming-Der Shieh, Hsin-Fu Lo, Ming-Hwa Sheu:
High-speed generation of LFSR signatures. Asian Test Symposium 2000: 222- - [c4]Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu:
An efficient approach for in-place scheduling of path metric update in Viterbi decoders. ISCAS 2000: 61-64
1990 – 1999
- 1999
- [c3]Che-Han Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu, Jia-Lin Sheu:
A VLSI architecture of fast high-radix modular multiplication for RSA cryptosystem. ISCAS (1) 1999: 500-503 - 1993
- [j1]Ming-Hwa Sheu, Yuan-Long Jeang, Jhing-Fa Wang, Jau-Yien Lee:
The determination of the cycle length in high level synthesis. Integr. 16(2): 131-148 (1993) - [c2]Ming-Hwa Sheu, Jhing-Fa Wang, Jau-Yien Lee, Lian-Ying Liu:
An Expandable Chip Desing for Gray-scale Morphological Operations. ISCAS 1993: 1563-1566 - [c1]Ming-Hwa Sheu, Jau-Yien Lee, Jhing-Fa Wang, An-Nan Suen, Lian-Ying Liu:
A High Throughput-Rate Architecture for 8*8 2-D DCT. ISCAS 1993: 1578-1590
Coauthor Index
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