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ORCID28th ASAP 2017: Seattle, WA, USA
- 28th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2017, Seattle, WA, USA, July 10-12, 2017. IEEE Computer Society 2017, ISBN 978-1-5090-4825-0
- Ken Eguro, Ryan Kastner
:
A message from the general chair and program chair. 1
Technical Papers Session 1 - Machine Learning
- Yuanfang Li, Ardavan Pedram:
CATERPILLAR: Coarse Grain Reconfigurable Architecture for accelerating the training of Deep Neural Networks. 1-10 - Abhinav Podili, Chi Zhang, Viktor K. Prasanna:
Fast and efficient implementation of Convolutional Neural Networks on FPGA. 11-18 - Aravind Vasudevan, Andrew Anderson, David Gregg:
Parallel Multi Channel convolution using General Matrix Multiplication. 19-24 - Mahdi Nazemi, Shahin Nazarian, Massoud Pedram:
High-performance FPGA implementation of equivariant adaptive separation via independence algorithm for Independent Component Analysis. 25-28
Session 2 - Security
- Bikash Poudel, Naresh Kumar Giri, Arslan Munir:
Design and comparative evaluation of GPGPU- and FPGA-based MPSoC ECU architectures for secure, dependable, and real-time automotive CPS. 29-36 - S. T. Choden Konigsmark, Deming Chen, Martin D. F. Wong:
High-Level Synthesis for side-channel defense. 37-44 - Amin Malekpour, Roshan G. Ragel, Aleksandar Ignjatovic, Sri Parameswaran:
DoSGuard: Protecting pipelined MPSoCs against hardware Trojan based DoS attacks. 45-52 - Chun-Jen Tsai, Cheng-Ju Lin, Cheng-Yang Chen, Yan-Hung Lin, Wei-Jhong Ji, Sheng-Di Hong:
Hardwiring the OS kernel into a Java application processor. 53-60 - Arman Pouraghily, Tilman Wolf, Russell Tessier:
Hardware support for embedded operating system security. 61-66
Session 3 - Image Processing
- Stefan Tabel, Korbinian Weikl, Walter Stechele:
Hardware-accelerated CCD readout smear correction for Fast Solar Polarimeter. 67-74 - Joe Edwards, Guy G. F. Lemieux:
Real-time object detection in software with custom vector instructions and algorithm changes. 75-82
Session 4 - Memory/Storage
- S. Navid Shahrouzi, Darshika G. Perera:
An efficient embedded multi-ported memory architecture for next-generation FPGAs. 83-90 - Yangguo Liu, Junlin Lu, Dong Tong, Xu Cheng:
A Staged Memory Resource Management Method for CMP systems. 91-98 - Wei Zhou, Dan Feng, Zhipeng Tan:
CFStore: Boosting Hybrid storage performance by device crossfire. 99-106 - Yanpeng Wang, Mei Wen, Chunyuan Zhang, Jie Lin:
RVNet: A fast and high energy efficiency network packet processing system on RISC-V. 107-110
Session 5 - High Performance Computing
- Yili Gong, Jia Tang, Wenhai Li, Zihui Ye:
Massive spatial query on the Kepler architecture. 111-118 - Binyang Li, Bo Li, Depei Qian:
PFSI.sw: A programming framework for sea ice model algorithms based on Sunway many-core processor. 119-126 - Jie Lin, Qingbo Wu, Yusong Tan, Jie Yu, Qi Zhang, Xiaoling Li, Lei Luo:
MicRun: A framework for scale-free graph algorithms on SIMD architecture of the Xeon Phi. 127-136 - Julien Hascoet, Karol Desnos, Jean-François Nezan, Benoît Dupont de Dinechin:
Hierarchical Dataflow Model for efficient programming of clustered manycore processors. 137-142 - Hongbing Tan, Haiyan Chen, Sheng Liu, Jianguo Wu:
Modeling and evaluation for gather/scatter operations in Vector-SIMD architectures. 143-148 - Achim Lösch, Marco Platzner:
reMinMin: A novel static energy-centric list scheduling approach based on real measurements. 149-154
Session 6 - Digital Signal Processing
- M. Akif Ozkan, Oliver Reiche, Frank Hannig, Jürgen Teich:
Hardware design and analysis of efficient loop coarsening and border handling for image processing. 155-163 - Rishan Senanayake, Namitha Liyanage, Sasindu Wijeratne, Sachille Atapattu, Kasun Athukorala, P. M. K. Tharaka, Geethan Karunaratne, R. M. A. U. Senarath, Ishantha Perera, Ashen Ekanayake, Ajith Pasqual:
High performance hardware architectures for Intra Block Copy and Palette Coding for HEVC screen content coding extension. 164-169 - Lin Li, Adrian E. Sapio, Jiahao Wu, Yanzhou Liu, Kyunghun Lee, Marilyn Wolf, Shuvra S. Bhattacharyya:
Design and implementation of adaptive signal processing systems using Markov decision processes. 170-175
Session 7 - Control Systems and Parallel Programming Languages
- Pei Zhang, Joseph Zambreno, Phillip H. Jones:
An embedded scalable linear model predictive hardware-based controller using ADMM. 176-183 - S. Alexander Chin, Noriaki Sakamoto, Allan Rui, Jim Zhao, Jin Hee Kim, Yuko Hara-Azumi, Jason Helge Anderson:
CGRA-ME: A unified framework for CGRA modelling and exploration. 184-189 - Jehandad Khan, Peter Athanas, Skip Booth, John Marshall:
OpenCL-based design pattern for line rate packet processing. 190-194 - Vinh Dang, Kevin Skadron:
Acceleration of Frequent Itemset Mining on FPGA using SDAccel and Vivado HLS. 195-200 - Lukas Sommer, Jens Korinth, Andreas Koch:
OpenMP device offloading to FPGA accelerators. 201-205
Posters Session 1
- Ruizhe Zhao, Tim Todman, Wayne Luk, Xinyu Niu:
DeepPump: Multi-pumping deep Neural Networks. 206 - Marcel Brand, Frank Hannig, Alexandru Tanase, Jürgen Teich:
Efficiency in ILP processing by using orthogonality. 207 - Jing Chen, Xue Liu:
A fast and accurate logarithm accelerator for scientific applications. 208 - Haoyu Liu, Huahu Xu, Honghao Gao, Danqi Chu:
Model checking cloud rendering system for the QoS evaluation. 209
Posters Session 2
- Yuanhong Huo, Dake Liu:
High-throughput area-efficient processor for 3GPP LTE cryptographic core algorithms. 210 - Juan Li, Zhengguo Chen, Zhiguang Chen, Nong Xiao, Fang Liu:
KV-FTL: A novel key-value based FTL scheme for large scale SSDs. 211
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