default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID27th FCCM 2019: San Diego, CA, USA
- 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2019, San Diego, CA, USA, April 28 - May 1, 2019. IEEE 2019, ISBN 978-1-7281-1131-5
Session 1: Open Source Tools
- David Shah, Eddie Hung, Clifford Wolf, Serge Bazanski, Dan Gisselquist, Miodrag Milanovic:
Yosys+nextpnr: An Open Source Framework from Verilog to Bitstream for Commercial FPGAs. 1-4 - Khoa Dang Pham, Malte Vesper, Dirk Koch, Eddie Hung:
EFCAD - An Embedded FPGA CAD Tool Flow for Enabling On-chip Self-Compilation. 5-8 - Dallon Glick, Jesse Grigg, Brent E. Nelson, Michael J. Wirthlin:
Maverick: A Stand-Alone CAD Flow for Partially Reconfigurable FPGA Modules. 9-16
Session 2: Machine Learning 1
- Liqiang Lu, Jiaming Xie, Ruirui Huang, Jiansong Zhang, Wei Lin, Yun Liang:
An Efficient Hardware Accelerator for Sparse Convolutional Neural Networks on FPGAs. 17-25 - Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides:
LUTNet: Rethinking Inference in FPGA Soft Logic. 26-34 - Seyedramin Rasoulinezhad, Hao Zhou, Lingli Wang, Philip H. W. Leong
:
PIR-DSP: An FPGA DSP Block Architecture for Multi-precision Deep Neural Networks. 35-44 - Cheng Luo, Man-Kit Sit, Hongxiang Fan, Shuanglong Liu, Wayne Luk, Ce Guo:
Towards Efficient Deep Neural Network Training by FPGA-Based Batch-Level Parallelism. 45-52
Session 3: Tools
- Dries Vercruyce, Elias Vansteenkiste, Dirk Stroobandt:
CRoute: A Fast High-Quality Timing-Driven Connection-Based FPGA Router. 53-60 - Leo Liu, Jay Weng, Nachiket Kapre:
RapidRoute: Fast Assembly of Communication Structures for FPGA Overlays. 61-64 - Matthew J. P. Walker, Jason Helge Anderson:
Generic Connectivity-Based CGRA Mapping via Integer Linear Programming. 65-73 - Ecenur Ustun, Shaojie Xiang, Jinny Gui, Cunxi Yu, Zhiru Zhang:
LAMDA: Learning-Assisted Multi-stage Autotuning for FPGA Design Closure. 74-77 - Nils Voss, Pablo Quintana, Oskar Mencer, Wayne Luk, Georgi Gaydadjiev:
Memory Mapping for Multi-die FPGAs. 78-86 - Ian Taras, Jason Helge Anderson:
Impact of FPGA Architecture on Area and Performance of CGRA Overlays. 87-95 - Weikang Qiao, Zhenman Fang, Mau-Chung Frank Chang, Jason Cong:
An FPGA-Based BWT Accelerator for Bzip2 Data Compression. 96-99
Session 4: Applications 1
- Shuzhen Qin, Qiang Liu, Bo Yu, Shaoshan Liu:
π-BA: Bundle Adjustment Acceleration on Embedded FPGAs with Co-observation Optimization. 100-108 - Milan Ceska, Vojtech Havlena, Lukás Holík, Jan Korenek, Ondrej Lengál, Denis Matousek, Jirí Matousek, Jakub Semric, Tomás Vojnar:
Deep Packet Inspection in FPGAs via Approximate Nondeterministic Automata. 109-117 - Marc Pfeifer, Philipp M. Scholl, Rainer Voigt, Bernd Becker:
Active Stereo Vision with High Resolution on an FPGA. 118-126 - Licheng Guo, Jason Lau, Zhenyuan Ruan, Peng Wei, Jason Cong:
Hardware Acceleration of Long Read Pairwise Overlapping in Genome Sequencing: A Race Between FPGA and GPU. 127-135 - Yu Wang, James C. Hoe, Eriko Nurvitadhi:
Processor Assisted Worklist Scheduling for FPGA Accelerated Graph Processing on a Shared-Memory Platform. 136-144
Session 5: Simulation and Infrastructure
- Jialiang Zhang, Yang Liu, Gaurav Jain, Yue Zha, Jonathan Ta, Jing Li:
MEG: A RISCV-Based System Simulation Infrastructure for Exploring Memory Optimization Using FPGAs and Hybrid Memory Cube. 145-153 - Gurshaant Singh Malik, Nachiket Kapre:
Enhancing Butterfly Fat Tree NoCs for FPGAs with Lightweight Flow Control. 154-162 - Konstantinos Iordanou, Oscar Palomar, John Mawer, Cosmin Gorgovan, Andy Nisbet, Mikel Luján:
SimAcc: A Configurable Cycle-Accurate Simulator for Customized Accelerators on CPU-FPGAs SoCs. 163-171
Session 6: Machine Learning 2
- Zhe Lin, Sharad Sinha, Wei Zhang:
Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA. 172-180 - Nitish Kumar Srivastava, Hongbo Rong, Prithayan Barua, Guanyu Feng, Huanqi Cao, Zhiru Zhang, David H. Albonesi, Vivek Sarkar, Wenguang Chen, Paul Petersen, Geoff Lowney, Adam Herr, Christopher J. Hughes, Timothy G. Mattson, Pradeep Dubey:
T2S-Tensor: Productively Generating High-Performance Spatial Hardware for Dense Tensor Computations. 181-189 - Mohsen Imani, Sahand Salamat, Behnam Khaleghi, Mohammad Samragh, Farinaz Koushanfar, Tajana Rosing:
SparseHD: Algorithm-Hardware Co-optimization for Efficient High-Dimensional Computing. 190-198 - Eriko Nurvitadhi, Dongup Kwon, Ali Jafari, Andrew Boutros, Jaewoong Sim, Phillip Tomson, Huseyin Sumbul, Gregory K. Chen, Phil C. Knag, Raghavan Kumar, Ram Krishnamurthy, Sergey Gribok, Bogdan Pasca, Martin Langhammer, Debbie Marr, Aravind Dasu:
Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs. 199-207
Session 7: Programming
- Haggai Eran, Lior Zeno, Zsolt István, Mark Silberstein:
Design Patterns for Code Reuse in HLS Packet Processing Pipelines. 208-217 - Jeferson Santiago da Silva, François-Raymond Boyer, J. M. Pierre Langlois:
Module-per-Object: A Human-Driven Methodology for C++-Based High-Level Synthesis Design. 218-226 - David B. Thomas:
Templatised Soft Floating-Point for High-Level Synthesis. 227-235 - Juan Escobedo, Mingjie Lin:
Exploiting Irregular Memory Parallelism in Quasi-Stencils through Nonlinear Transformation. 236-244
Session 8: Applications 2
- Tianqi Wang, Tong Geng, Xi Jin, Martin C. Herbordt:
FP-AMR: A Reconfigurable Fabric Framework for Adaptive Mesh Refinement Applications. 245-253 - Yushan Su, Michael Anderson, Jonathan I. Tamir, Michael Lustig, Kai Li:
Compressed Sensing MRI Reconstruction on Intel HARPv2. 254-257 - Qingqing Xiong, Rushi Patel, Chen Yang, Tong Geng, Anthony Skjellum, Martin C. Herbordt:
GhostSZ: A Transparent FPGA-Accelerated Lossy Compression Framework. 258-266 - Maheshwaran Ramesh Babu, Farah Naz Taher, Anjana Balachandran, Benjamin Carrión Schäfer:
Efficient Hardware Acceleration for Design Diversity Calculation to Mitigate Common Mode Failures. 267-270
Session 9: Security and Reliability
- Linda L. Shen, Ibrahim Ahmed, Vaughn Betz:
Fast Voltage Transients on FPGAs: Impact and Mitigation Strategies. 271-279 - Siam U. Hussain, Farinaz Koushanfar:
FASE: FPGA Acceleration of Secure Function Evaluation. 280-288
Session 10: Arithmetic
- Eric Matthews, Alec Lu, Zhenman Fang, Lesley Shannon:
Rethinking Integer Divider Design for FPGA-Based Soft-Processors. 289-297 - Martin Langhammer, Bogdan Pasca, Gregg Baeckler:
High Precision, High Performance FPGA Adders. 298-306
Poster Session 1: Tools
- Rafael Zamacola, Alberto García-Martínez, Javier Mora, Andrés Otero, Eduardo de la Torre:
Automated Tool and Runtime Support for Fine-Grain Reconfiguration in Highly Flexible Reconfigurable Systems. 307 - Qijing Huang, Ameer Haj-Ali, William S. Moses, John Xiang, Ion Stoica, Krste Asanovic, John Wawrzynek:
AutoPhase: Compiler Phase-Ordering for HLS with Deep Reinforcement Learning. 308 - Norbert Deak, Octavian Cret, Horia Hedesiu:
Efficient FPGA Floorplanning for Partial Reconfiguration-Based Applications. 309 - Michail Papadimitriou, Juan Fumero, Athanasios Stratikopoulos, Christos Kotselidis:
Towards Prototyping and Acceleration of Java Programs onto Intel FPGAs. 310 - Varun Sharma, Naif Tarafdar, Paul Chow:
Sonar: Writing Testbenches through Python. 311 - Minghua Shen, Nong Xiao:
Raparo: Resource-Level Angle-Based Parallel Routing for FPGAs. 312 - Francesco Peverelli, Marco Rabozzi, Salvatore Cardamone, Emanuele Del Sozzo, Alex J. W. Thom, Marco D. Santambrogio, Lorenzo Di Tucci:
Automated Acceleration of Dataflow-Oriented C Applications on FPGA-Based Systems. 313 - Marco Siracusa, Marco Rabozzi, Emanuele Del Sozzo, Marco D. Santambrogio, Lorenzo Di Tucci:
Automated Design Space Exploration and Roofline Analysis for FPGA-Based HLS Applications. 314 - Florian Faissole, George A. Constantinides, David B. Thomas:
Formalizing Loop-Carried Dependencies in Coq for High-Level Synthesis. 315
Poster Session 2: Neural Networks and Vision
- Zheming Jin, Hal Finkel:
Exploring the Random Network of Hodgkin and Huxley Neurons with Exponential Synaptic Conductances on OpenCL FPGA Platform. 316 - Ke Xu, Xiaoyun Wang, Dong Wang:
A Scalable OpenCL-Based FPGA Accelerator for YOLOv2. 317 - Kota Yoshida, Takaya Kubota, Mitsuru Shiozaki, Takeshi Fujino:
Model-Extraction Attack Against FPGA-DNN Accelerator Utilizing Correlation Electromagnetic Analysis. 318 - Cheng Fu, Shilin Zhu, Huili Chen, Farinaz Koushanfar, Hao Su, Jishen Zhao:
SimBNN: A Similarity-Aware Binarized Neural Network Acceleration Framework. 319 - Yuke Wang, Zhaorui Zeng, Boyuan Feng, Lei Deng, Yufei Ding:
KPynq: A Work-Efficient Triangle-Inequality Based K-Means on FPGA. 320 - Lili Liu, Xiaoqiang Xiang, Yuxiang Xie, Yongjie Li, Bo Yan, Jun Zhou:
A High Throughput and Energy-Efficient Retina-Inspired Tone Mapping Processor. 321 - Samah Rahamneh, Lina Sawalha:
An OpenCL-Based Acceleration for Canny Algorithm Using a Heterogeneous CPU-FPGA Platform. 322
Poster Session 3: Networking and Resource Sharing
- Jakub Cabal, Pavel Benácek, Jana Foltova, Juraj Holub:
Scalable P4 Deparser for Speeds Over 100 Gbps. 323 - Sang-Woo Jun, Arvind Arvind:
Wire-Speed Multirate Accelerator for Aggregation Operations on Sorted Data. 324 - Zhe Pan, Xiaohong Jiang, Jian Wu, Xiang Li:
Hybrid XML Parser Based on Software and Hardware Co-design. 325 - Han Chen, Sergey Madaminov, Michael Ferdman, Peter A. Milder:
Sorting Large Data Sets with FPGA-Accelerated Samplesort. 326 - Martin Geier, Dominik Faller, Marian Brändle, Samarjit Chakraborty:
Cost-Effective Energy Monitoring of a Zynq-Based Real-Time System Including Dual Gigabit Ethernet. 327 - William Hunter, Christopher McCarty, Lee Lerner:
Improved Techniques for Sensing Intra-Device Side Channel Leakage. 328 - Sameh Attia, Vaughn Betz:
Safe Task Interruption for FPGAs. 329
Poster Session 4: Applications
- Zheming Jin, Hal Finkel:
OpenCL Kernel Vectorization on the CPU, GPU, and FPGA: A Case Study with Frequent Pattern Compression. 330 - Atsutake Kosuge, Keisuke Yamamoto, Yukinori Akamine, Taizo Yamawaki, Takashi Oshima:
A 4.8x Faster FPGA-Based Iterative Closest Point Accelerator for Object Pose Estimation of Picking Robot Applications. 331 - Dan Pritsker, Colman Cheung:
Monobit Wideband Receiver with Integrated Dithering in FPGA. 332 - Alberto Zeni, Matteo Crespi, Lorenzo Di Tucci, Marco D. Santambrogio:
An FPGA-Based Computing Infrastructure Tailored to Efficiently Scaffold Genome Sequences. 333 - Glenn G. Ko, Yuji Chai, Rob A. Rutenbar, David Brooks, Gu-Yeon Wei:
FlexGibbs: Reconfigurable Parallel Gibbs Sampling Accelerator for Structured Graphs. 334 - Jian Fang, Jianyu Chen, Jinho Lee, Zaid Al-Ars, H. Peter Hofstee:
A Fine-Grained Parallel Snappy Decompressor for FPGAs Using a Relaxed Execution Model. 335 - Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones, Kristof Denolf, Jack Lo, Kees A. Vissers:
Analyzing the Energy-Efficiency of Vision Kernels on Embedded CPU, GPU and FPGA Platforms. 336 - Dajung Lee, Andrei Hagiescu, Dan Pritsker:
Large-Scale and High-Throughput QR Decomposition on an FPGA. 337 - Sergiu Mosanu, Xinfei Guo, Mohamed El-Hadedy, Lorena Anghel, Mircea Stan:
Flexi-AES: A Highly-Parameterizable Cipher for a Wide Range of Design Constraints. 338
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-02-05 20:19 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
