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2020 – today
- 2024
[j29]Juan Encinas
, Alfonso Rodríguez, Andrés Otero, Eduardo de la Torre:
Data-driven modeling of reconfigurable multi-accelerator systems under dynamic workloads. Microprocess. Microsystems 107: 105050 (2024)- 2023
- [j28]José L. Núñez-Yáñez, J. Andrés Otero, Eduardo de la Torre:
Dynamically reconfigurable variable-precision sparse-dense matrix acceleration in Tensorflow Lite. Microprocess. Microsystems 98: 104801 (2023) - [c63]Andrés Otero, Guillermo Sanllorente, Eduardo de la Torre, José L. Núñez-Yáñez:
Evolutionary FPGA-Based Spiking Neural Networks for Continual Learning. ARC 2023: 260-274 - [i1]José L. Núñez-Yáñez, Andrés Otero, Eduardo de la Torre:
Dynamically Reconfigurable Variable-precision Sparse-Dense Matrix Acceleration in Tensorflow Lite. CoRR abs/2304.08211 (2023) - 2022
- [j27]Alfonso Rodríguez, Andrés Otero, Marco Platzner, Eduardo de la Torre:
Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs. IEEE Trans. Computers 71(11): 2903-2914 (2022) - [c62]Javier Laserna, Andrés Otero, Eduardo de la Torre:
A Multi-FPGA Scalable Framework for Deep Reinforcement Learning Through Neuroevolution. ARC 2022: 47-61 - [c61]Daniel Vázquez, Alfonso Rodríguez, Andrés Otero, Eduardo de la Torre:
Extending RISC-V Processor Datapaths with Multi-Grain Reconfigurable Overlays. DCIS 2022: 1-6 - [c60]Rafael Zamacola, Andrés Otero, Alfonso Rodríguez, Eduardo de la Torre:
Just-In-Time Composition of Reconfigurable Overlays (Invited Talk). PARMA-DITAM@HiPEAC 2022: 2:1-2:13 - 2021
- [j26]Rodrigo Marino, Cristian Wisultschew, Andrés Otero, José Manuel Lanza-Gutiérrez, Jorge Portilla, Eduardo de la Torre:
A Machine-Learning-Based Distributed System for Fault Diagnosis With Scalable Detection Quality in Industrial IoT. IEEE Internet Things J. 8(6): 4339-4352 (2021) - [j25]Rafael Zamacola, Andrés Otero, Eduardo de la Torre:
Multi-grain reconfigurable and scalable overlays for hardware accelerator composition. J. Syst. Archit. 121: 102302 (2021) - [c59]Juan Encinas, Alfonso Rodríguez, Andrés Otero, Eduardo de la Torre:
Run-Time Monitoring and ML-Based Modeling in Reconfigurable Multi-Accelerator Systems. DCIS 2021: 1-7 - 2020
- [j24]Arturo Perez, Alfonso Rodríguez, Andrés Otero, David González Arjona, Álvaro Jiménez-Peralo, Miguel Ángel Verdugo, Eduardo de la Torre:
Run-Time Reconfigurable MPSoC-Based On-Board Processor for Vision-Based Space Navigation. IEEE Access 8: 59891-59905 (2020) - [j23]Leonardo Suriano, Andrés Otero, Alfonso Rodríguez, Manuel Sánchez-Renedo, Eduardo de la Torre:
Exploiting Multi-Level Parallelism for Run-Time Adaptive Inverse Kinematics on Heterogeneous MPSoCs. IEEE Access 8: 118707-118724 (2020) - [j22]Rafael Zamacola, Andrés Otero, Alberto García-Martínez, Eduardo de la Torre:
An Integrated Approach and Tool Support for the Design of FPGA-Based Multi-Grain Reconfigurable Systems. IEEE Access 8: 202133-202152 (2020) - [c58]Alberto García Ortiz, Rafael Zamacola, Alfonso Rodríguez, Andrés Otero, Eduardo de la Torre:
Automated Toolchain for Enhanced Productivity in Reconfigurable Multi-accelerator Systems. ARC 2020: 45-60 - [c57]Leonardo Suriano, David Lima, Eduardo de la Torre:
Accelerating a Classic 3D Video Game on Heterogeneous Reconfigurable MPSoCs. ARC 2020: 136-150
2010 – 2019
- 2019
- [j21]Alfonso Rodríguez, Lucana Santos, Roberto Sarmiento, Eduardo de la Torre:
Scalable Hardware-Based On-Board Processing for Run-Time Adaptive Lossless Hyperspectral Compression. IEEE Access 7: 10644-10652 (2019) - [j20]Javier Mora, Rubén Salvador, Eduardo de la Torre:
On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming. Genet. Program. Evolvable Mach. 20(2): 155-186 (2019) - [j19]Leonardo Suriano, Florian Arrestier, Alfonso Rodríguez, Julien Heulot, Karol Desnos, Maxime Pelcat, Eduardo de la Torre:
DAMHSE: Programming heterogeneous MPSoCs with hardware acceleration using dataflow-based design space exploration and automated rapid prototyping. Microprocess. Microsystems 71 (2019) - [c56]Luca Fanni, Leonardo Suriano, Claudio Rubattu, Pablo Sánchez, Eduardo de la Torre, Francesca Palumbo:
A Dataflow Implementation of Inverse Kinematics on Reconfigurable Heterogeneous MPSoC. CPS Summer School, PhD Workshop 2019: 107-118 - [c55]Rodrigo Marino, Sergio Quintero, José Manuel Lanza-Gutiérrez, Teresa Riesgo, Miguel Holgado, Jorge Portilla, Eduardo de la Torre:
Hardware Accelerator for Ethanol Detection in Water Media based on Machine Learning Techniques. DCIS 2019: 1-6 - [c54]Cristian Wisultschew, Andrés Otero, Jorge Portilla, Eduardo de la Torre:
Artificial Vision on Edge IoT Devices: A Practical Case for 3D Data Classification. DCIS 2019: 1-7 - [c53]Rafael Zamacola, Alberto García-Martínez, Javier Mora, Andrés Otero, Eduardo de la Torre:
Automated Tool and Runtime Support for Fine-Grain Reconfiguration in Highly Flexible Reconfigurable Systems. FCCM 2019: 307 - [c52]Alberto García Ortiz, Alfonso Rodríguez, Andrés Otero, Eduardo de la Torre:
Data Transfer Modeling and Optimization in Reconfigurable Multi-Accelerator Systems. ReCoSoC 2019: 20-26 - [c51]Francesca Palumbo, Tiziana Fanni, Carlo Sau, Alfonso Rodríguez, Daniel Madroñal, Karol Desnos, Antoine Morvan, Maxime Pelcat, Claudio Rubattu, Raquel Lazcano, Luigi Raffo, Eduardo de la Torre, Eduardo Juárez, César Sanz, Pablo Sanchez de Rojas:
Hardware/Software Self-adaptation in CPS: The CERBERO Project Approach. SAMOS 2019: 416-428 - 2018
- [j18]Javier Mora, Eduardo de la Torre:
Accelerating the evolution of a systolic array-based evolvable hardware system. Microprocess. Microsystems 56: 144-156 (2018) - [j17]Alberto García Ortiz, Alfonso Rodríguez, Raúl Guerra, Sebastián López, Andrés Otero, Roberto Sarmiento, Eduardo de la Torre:
A Runtime-Scalable and Hardware-Accelerated Approach to On-Board Linear Unmixing of Hyperspectral Images. Remote. Sens. 10(11): 1790 (2018) - [j16]Alfonso Rodríguez, Juan Valverde, Jorge Portilla, Andrés Otero, Teresa Riesgo, Eduardo de la Torre:
FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo3 Framework. Sensors 18(6): 1877 (2018) - [c50]Arturo Perez, Andrés Otero, Eduardo de la Torre:
Performance Analysis of SEE Mitigation Techniques on Zynq Ultrascale + Hardened Processing Fabrics. AHS 2018: 51-58 - [c49]Tiziana Fanni, Alfonso Rodríguez, Carlo Sau, Leonardo Suriano, Francesca Palumbo, Luigi Raffo, Eduardo de la Torre:
Multi-Grain Reconfiguration for Advanced Adaptivity in Cyber-Physical Systems. ReConFig 2018: 1-8 - [c48]Rafael Zamacola, Alberto García-Martínez, Javier Mora, Andrés Otero, Eduardo de la Torre:
IMPRESS: Automated Tool for the Implementation of Highly Flexible Partial Reconfigurable Systems with Xilinx Vivado. ReConFig 2018: 1-8 - [c47]Leonardo Suriano, Daniel Madroñal, Alfonso Rodríguez, Eduardo Juárez, César Sanz, Eduardo de la Torre:
A Unified Hardware/Software Monitoring Method for Reconfigurable Computing Architectures Using PAPI. ReCoSoC 2018: 1-8 - 2017
- [c46]Arturo Perez, Leonardo Suriano, Andrés Otero, Eduardo de la Torre:
Dynamic reconfiguration under RTEMS for fault mitigation and functional adaptation in SRAM-based SoPCs for space systems. AHS 2017: 40-47 - [c45]Michael Masin, Francesca Palumbo, Hans Myrhaug, J. A. de Oliveira Filho, M. Pastena, Maxime Pelcat, Luigi Raffo, Francesco Regazzoni, A. A. Sanchez, Antonella Toffetti, Eduardo de la Torre, Katiuscia Zedda:
Cross-layer design of reconfigurable cyber-physical systems. DATE 2017: 740-745 - [c44]Leonardo Suriano, Alfonso Rodríguez, Karol Desnos, Maxime Pelcat, Eduardo de la Torre:
Analysis of a heterogeneous multi-core, multi-hw-accelerator-based system designed using PREESM and SDSoC. ReCoSoC 2017: 1-7 - 2016
- [j15]René Cumplido, Peter Athanas, Eduardo de la Torre:
Introduction to the Special Section on FPGAs Technology and Applications. Comput. Electr. Eng. 49: 67-68 (2016) - [j14]Teresa Cervero, Andrés Otero, Sebastián López, Eduardo de la Torre, Gustavo Marrero Callicó, Teresa Riesgo, Roberto Sarmiento:
A scalable H.264/AVC deblocking filter architecture. J. Real Time Image Process. 12(1): 81-105 (2016) - 2015
- [j13]Wei He, Shivam Bhasin, Andrés Otero, Tarik Graba, Eduardo de la Torre, Jean-Luc Danger:
Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis. IET Inf. Secur. 9(1): 1-13 (2015) - [j12]René Cumplido, Eduardo de la Torre, Claudia Feregrino Uribe, Michael J. Wirthlin:
Introduction to Special issue on Reconfigurable computing and FPGAs. Microprocess. Microsystems 39(7): 541-542 (2015) - [j11]Eduardo de la Torre, Jorge Portilla, Teresa Riesgo:
Letter from the guest editors of the special issue on DCIS 2014. Microprocess. Microsystems 39(8): 919 (2015) - [c43]Filip Veljkovic, Teresa Riesgo, Eduardo de la Torre:
Adaptive reconfigurable voting for enhanced reliability in medium-grained fault tolerant architectures. AHS 2015: 1-8 - [c42]Alfonso Rodríguez, Juan Valverde, Cesar Castanares, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo:
Live demonstration: A dynamically adaptable image processing application running in an FPGA-based WSN platform. ISCAS 2015: 1902 - [c41]Alfonso Rodríguez, Juan Valverde, Eduardo de la Torre:
Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAs. ReConFig 2015: 1-7 - [c40]Javier Mora, Andrés Otero, Eduardo de la Torre, Teresa Riesgo:
Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs. ReCoSoC 2015: 1-7 - [c39]Alberto García Ortiz, Daniel Gregorek, Eduardo de la Torre, Juha Plosila:
Message from the chairs. ReCoSoC 2015: 1 - [c38]Alfonso Rodríguez, Juan Valverde, Cesar Castanares, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo:
Execution modeling in self-aware FPGA-based architectures for efficient resource management. ReCoSoC 2015: 1-8 - 2014
- [j10]Peter Athanas, René Cumplido, Eduardo de la Torre:
Introduction to the special issue on FPGA Technology and Applications. Comput. Electr. Eng. 40(4): 1143-1145 (2014) - [j9]Peter M. Athanas, René Cumplido, Claudia Feregrino Uribe, Eduardo de la Torre:
Introduction to Special issue on FPGA Devices and Applications. Microprocess. Microsystems 38(8): 843-844 (2014) - [j8]Wei He, Andrés Otero, Eduardo de la Torre, Teresa Riesgo:
Customized and automated routing repair toolset towards side-channel analysis resistant dual rail logic. Microprocess. Microsystems 38(8): 899-910 (2014) - [c37]Blanca López, Juan Valverde, Eduardo de la Torre, Teresa Riesgo:
Power-aware multi-objective evolvable hardware system on an FPGA. AHS 2014: 61-68 - [c36]Filip Veljkovic, Teresa Riesgo, Eduardo de la Torre, Raul Regada, Luis Berrojo:
A run time adaptive architecture to trade-off performance for fault tolerance applied to a DVB on-board processor. AHS 2014: 143-150 - [c35]Juan Valverde, Alfonso Rodríguez, Julio Camarero, Andrés Otero, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo:
A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical Systems. FPL 2014: 1-4 - [c34]Chenyang Tu, Wei He, Neng Gao, Eduardo de la Torre, Zeyi Liu, Limin Liu:
A Progressive Dual-Rail Routing Repair Approach for FPGA Implementation of Crypto Algorithm. ISPEC 2014: 217-231 - [c33]Alfonso Rodríguez, Juan Valverde, Eduardo de la Torre, Teresa Riesgo:
Dynamic management of multikernel multithread accelerators using Dynamic Partial Reconfiguration. ReCoSoC 2014: 1-7 - [e1]Eduardo de la Torre, Sébastien Pillement:
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, DASIP 2014, Madrid, Spain, October 8-10, 2014. IEEE 2014, ISBN 979-10-92279-06-1 [contents] - 2013
- [j7]Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina:
Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing. IEEE Trans. Computers 62(8): 1481-1493 (2013) - [c32]Javier Mora, Angel Gallego, Andrés Otero, Eduardo de la Torre, Teresa Riesgo:
Noise-agnostic adaptive image filtering without training references on an evolvable hardware platform. DASIP 2013: 182-189 - [c31]Javier Mora, Angel Gallego, Andrés Otero, Blanca López, Eduardo de la Torre, Teresa Riesgo:
A noise-agnostic self-adaptive image processing application based on evolvable hardware. DASIP 2013: 351-352 - [c30]Angel Gallego, Javier Mora, Andrés Otero, Blanca López, Eduardo de la Torre, Teresa Riesgo:
A self-adaptive image processing application based on evolvable and scalable hardware. FPL 2013: 1 - [c29]Angel Gallego, Javier Mora, Andrés Otero, Rubén Salvador, Eduardo de la Torre, Teresa Riesgo:
A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing Arrays. IPDPS Workshops 2013: 182-191 - [c28]Angel Gallego, Javier Mora, Andrés Otero, Eduardo de la Torre, Teresa Riesgo:
A scalable evolvable hardware processing array. ReConFig 2013: 1-7 - 2012
- [j6]Juan Valverde, Andrés Otero, Miguel Lopez, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo:
Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks. Sensors 12(3): 2667-2692 (2012) - [c27]Wei He, Eduardo de la Torre, Teresa Riesgo:
An Interleaved EPE-Immune PA-DPL Structure for Resisting Concentrated EM Side Channel Attacks on FPGA Implementation. COSADE 2012: 39-53 - [c26]Iakovos Mavroidis, Ioannis Mavroidis, Ioannis Papaefstathiou, Luciano Lavagno, Mihai T. Lazarescu, Eduardo de la Torre, Florian Schäfer:
FASTCUDA: Open Source FPGA Accelerator & Hardware-Software Codesign Toolset for CUDA Kernels. DSD 2012: 343-348 - [c25]Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina:
Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration. FPL 2012: 547-550 - [c24]Wei He, Andrés Otero, Eduardo de la Torre, Teresa Riesgo:
Automatic generation of identical routing pairs for FPGA implemented DPL logic. ReConFig 2012: 1-6 - [c23]Andrés Otero, Eduardo de la Torre, Teresa Riesgo:
Dreams: A tool for the design of dynamically reconfigurable embedded and modular systems. ReConFig 2012: 1-8 - [c22]Miguel Lombardo, Julio Camarero, Juan Valverde, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo:
Power management techniques in an FPGA-based WSN node for high performance applications. ReCoSoC 2012: 1-8 - 2011
- [c21]Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina:
Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support. AHS 2011: 184-191 - [c20]Andrés Otero, Rubén Salvador, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina:
A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems. AHS 2011: 336-343 - [c19]Andrés Otero, Eduardo de la Torre, Teresa Riesgo, Teresa Cervero, Sebastián López, Gustavo Marrero Callicó, Roberto Sarmiento:
Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs. FPL 2011: 369-375 - [c18]Teresa Cervero, Andrés Otero, Sebastián López, Eduardo de la Torre, Gustavo Marrero Callicó, Roberto Sarmiento, Teresa Riesgo:
A novel scalable Deblocking Filter architecture for H.264/AVC and SVC video codecs. ICME 2011: 1-6 - [c17]Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Lukás Sekanina, Teresa Riesgo:
Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems. ReConFig 2011: 164-169 - [c16]Wei He, Eduardo de la Torre, Teresa Riesgo:
A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations. ReConFig 2011: 217-222 - 2010
- [j5]Jorge Portilla, Andrés Otero, Eduardo de la Torre, Teresa Riesgo, Oliver Stecklina, Steffen Peter, Peter Langendörfer:
Adaptable Security in Wireless Sensor Networks by Using Reconfigurable ECC Hardware Coprocessors. Int. J. Distributed Sens. Networks 6(1) (2010) - [j4]Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo:
Reconfigurable Networks on Chip: DRNoC architecture. J. Syst. Archit. 56(7): 293-302 (2010) - [c15]Andrés Otero, Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo:
Generic Systolic Array for Run-Time Scalable Cores. ARC 2010: 4-16 - [c14]Andrés Otero, Angel Morales-Cas, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo:
A Modular Peripheral to Support Self-Reconfiguration in SoCs. DSD 2010: 88-95 - [c13]Andrés Otero, Eduardo de la Torre, Teresa Riesgo, Yana Esteves Krasteva:
Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs. FPL 2010: 70-76
2000 – 2009
- 2008
- [c12]Yana Esteves Krasteva, Francisco Criado, Eduardo de la Torre, Teresa Riesgo:
A Fast Emulation-Based NoC Prototyping Framework. ReConFig 2008: 211-216 - 2007
- [j3]Eduardo Peña, Eduardo de la Torre, Angel de Castro, Teresa Riesgo:
A digital system to emulate wireless networks. IET Comput. Digit. Tech. 1(5): 444-450 (2007) - [c11]Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo:
Reconfigurable Heterogeneous Communications and Core Reallocation for Dynamic HW Task Management. ISCAS 2007: 873-876 - 2006
- [j2]Jorge Portilla, Angel de Castro, Eduardo de la Torre, Teresa Riesgo:
A Modular Architecture for Nodes in Wireless Sensor Networks. J. Univers. Comput. Sci. 12(3): 328-339 (2006) - [c10]Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo, Didier Joly:
Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems. FPL 2006: 1-4 - [c9]Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo:
Partial Reconfiguration for Core Reallocation and Flexible Communications. ReCoSoC 2006: 91-97 - 2005
- [c8]Yana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo:
Flexible Core Reallocation for Virtex II Structures. ERSA 2005: 189-195 - [c7]Yana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo:
Straight Method for Reallocation of Complex Cores by Dynamic Reconfiguration in Virtex II FPGAs. IEEE International Workshop on Rapid System Prototyping 2005: 77-83 - 2004
- [c6]Mario García-Valderas, Eduardo de la Torre, F. Ariza, Teresa Riesgo:
Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion. FPL 2004: 1057-1061 - 2000
- [c5]Eduardo de la Torre, Teresa Riesgo, Javier Uceda, E. Macip, M. Rizzi:
Highly Configurable Control Boards: A Tool and a Design Experience. IEEE International Workshop on Rapid System Prototyping 2000: 174-
1990 – 1999
- 1999
- [j1]Teresa Riesgo, Yago Torroja, Eduardo de la Torre:
Design methodologies based on hardware description languages. IEEE Trans. Ind. Electron. 46(1): 3-12 (1999) - 1998
- [c4]Teresa Riesgo, Yago Torroja, Eduardo de la Torre, Javier Uceda:
Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models. DATE 1998: 955-956 - 1996
- [c3]Eduardo de la Torre, J. Calvo, Javier Uceda:
Model generation of test logic for macrocell based designs. EURO-DAC 1996: 456-461 - 1993
- [c2]Maria José Aguado, Miguel Miranda, Eduardo de la Torre, Carlos A. López-Barrio:
A dynamic communication strategy for the distributed ATPG system DPLATON. EURO-DAC 1993: 271-276 - [c1]Maria José Aguado, Eduardo de la Torre, Miguel Miranda, Carlos A. López-Barrio:
Distributed Implementation of an ATPG System Using Dynamic Fault Allocation. ITC 1993: 409-418
Coauthor Index
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