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ORCIDMEMSYS 2017: Alexandria, VA, USA
- Bruce L. Jacob:
Proceedings of the International Symposium on Memory Systems, MEMSYS 2017, Alexandria, VA, USA, October 02 - 05, 2017. ACM 2017, ISBN 978-1-4503-5335-9
Processing in and or near memory
- Jason Cong, Zhenman Fang, Michael Gill, Farnoosh Javadi, Glenn Reinman:
AIM: accelerating computational genomics through scalable and noninvasive accelerator-interposed memory. 3-14 - Mats Rimborg
, Pedro Trancoso, Gunnar Carlstedt:
PHOENIX: efficient computation in memory. 15-25 - G. Scott Lloyd, Maya B. Gokhale:
Near memory key/value lookup acceleration. 26-33 - Jonathan C. Beard:
The sparse data reduction engine: chopping sparse data one byte at a time. 34-48 - Chad D. Kersey, Hyesoon Kim, Sudhakar Yalamanchili:
Lightweight SIMT core designs for intelligent 3D stacked DRAM. 49-59 - Ahsan Javed Awan, Moriyoshi Ohara, Eduard Ayguadé, Kazuaki Ishizaki, Mats Brorsson, Vladimir Vlassov:
Identifying the potential of near data processing for apache spark. 60-67
DRAM technology details
- Patrick Siegl, Rainer Buchty, Mladen Berekovic:
A bandwidth accurate, flexible and rapid simulating multi-HMC modeling tool. 71-82 - Michael B. Healy, Seokin Hong:
CramSim: controller and memory simulator. 83-85 - Radhika Jagtap, Matthias Jung, Wendy Elsasser, Christian Weis, Andreas Hansson, Norbert Wehn:
Integrating DRAM power-down modes in gem5 and quantifying their impact. 86-95 - Alirad Malek, Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis:
Odd-ECC: on-demand DRAM error correcting codes. 96-111 - Kartikay Garg, Jeffrey S. Young:
Evaluating hybrid memory cube infrastructure to support high-performance sparse algorithms. 112-114 - Deepak M. Mathew, Éder F. Zulian, Matthias Jung, Kira Kraft, Christian Weis, Bruce L. Jacob, Norbert Wehn:
Using run-time reverse-engineering to optimize DRAM refresh. 115-124
Cache architectures and management
- Christopher Garman, Xiaochen Guo, Michael F. Spear:
A study of unnecessary write backs. 127-129 - Nafiul Alam Siddique, Abdel-Hameed A. Badawy:
SprBlk cache: enabling fault resilience at low voltages. 130-140 - Fazal Hameed, Christian Menard, Jerónimo Castrillón:
Efficient STT-RAM last-level-cache architecture to replace DRAM cache. 141-151 - Nafiul Alam Siddique, Abdel-Hameed A. Badawy, Jeanine E. Cook, David Resnick:
LMStr: exploring shared hardware controlled scratchpad memory for multicores. 152-165 - Elizabeth Reed, Alaa R. Alameldeen, Helia Naeimi, Patrick Stolt:
Probabilistic replacement strategies for improving the lifetimes of NVM-based caches. 166-176 - Mengjie Li, Matheus Ogleari, Jishen Zhao:
Logging in persistent memory: to cache, or not to cache? 177-179
Next-generation memory technologies
- Frederick A. Ware, Liji Gopalakrishnan, Eric Linstadt, Sally A. McKee, Thomas Vogelsang, Kenneth L. Wright, Craig Hampel, Gary Bronner:
Do superconducting processors really need cryogenic memories?: the case for cold DRAM. 183-188 - Swamit S. Tannu, Douglas M. Carmean, Moinuddin K. Qureshi:
Cryogenic-DRAM based memory system for scalable quantum computers: a feasibility study. 189-195 - Kfir Mizrachi, Ilan Bloom, Yuval Cassuto:
Memory reliability for cells with strong bit-coupling interference. 196-204 - Seyed Mohammad Seyedzadeh, Donald Kline Jr., Alex K. Jones, Rami G. Melhem:
Mitigating bitline crosstalk noise in DRAM memories. 205-216 - Mehrdad Biglari, Dietmar Fey:
Memristive voltage divider: a bipolar ReRAM-based unit for non-volatile flip-flops. 217-222 - Heba Saadeldeen, Zhaoxia Deng, Timothy Sherwood, Frederic T. Chong:
Thermal-aware, heterogeneous materials for improved energy and reliability in 3D PCM architectures. 223-236
Software and hardware optimization techniques
- Chencheng Ye, Chen Ding, Hai Jin:
Memory equalizer for lateral management of heterogeneous memory. 239-248 - Rakhi Hemani, Subhasis Banerjee, Apala Guha:
The interaction of last-level-cache mechanisms on modern processors. 249-250 - Thaleia Dimitra Doudali, Ada Gavrilovska:
CoMerge: toward efficient data placement in shared heterogeneous memory systems. 251-261 - Edgar A. León:
mpibind: a memory-centric affinity algorithm for hybrid applications. 262-264 - Ankit Agrawal, Gerhard Fohler:
DRAM-related challenges in task scheduling with timing predictability on COTS multi-cores for safety-critical systems. 265-267 - Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi:
BATMAN: techniques for maximizing system bandwidth of memory systems with stacked-DRAM. 268-280
Thinking outside the box
- Kazi Asifuzzaman, Rommel Sánchez Verdejo, Petar Radojkovic:
Enabling a reliable STT-MRAM main memory simulation. 283-292 - Blaise-Pascal Tine, Sudhakar Yalamanchili:
Pagevault: securing off-chip memory using page-based authentication. 293-304 - Yuan Zeng, Xiaochen Guo:
Long short term memory based hardware prefetcher: a case study. 305-311 - Fernando Martin del Campo, Paul Chow:
Task replication and control for highly parallel in-memory stores. 312-326 - Mohammad A. Qayum, Abdel-Hameed A. Badawy, Jeanine E. Cook:
DyAdHyTM: a low overhead dynamically adaptive hybrid transactional memory with application to large graphs. 327-336 - Dmitry Knyaginin, Per Stenström:
Rock: a framework for pruning the design space of hybrid main memory systems. 337-347
Management of non-volatile memories
- Bahareh Pourshirazi, Zhichun Zhu:
NEMO: an energy-efficient hybrid main memory system for mobile devices. 351-362 - Andrés Amaya García, René de Jong, William Wang, Stephan Diestelhorst:
Composing lifetime enhancing techniques for non-volatile main memories. 363-373 - Yanqin Jin, Hung-Wei Tseng, Yannis Papakonstantinou, Steven Swanson:
Improving SSD lifetime with byte-addressable metadata. 374-384 - Mohammad Khavari Tavana, Amir Kavyan Ziabari, Mohammad Arjomand, Mahmut T. Kandemir, Chita R. Das, David R. Kaeli:
REMAP: a reliability/endurance mechanism for advancing PCM. 385-398 - Viacheslav V. Fedorov, Jinchun Kim, Mian Qin, Paul V. Gratz, A. L. Narasimha Reddy:
Speculative paging for future NVM storage. 399-410 - Amro Awad, Simon D. Hammond, Clay Hughes, Arun Rodrigues, K. Scott Hemmert, Robert J. Hoekstra:
Performance analysis for using non-volatile memory DIMMs: opportunities and challenges. 411-420
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