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ORCIDIntegration, Volume 69
Volume 69, November 2019
- Saeideh Kabirpour
, Mohsen Jalali:
A highly linear current-starved VCO based on a linearized current control mechanism. 1-9 - Kunwar Singh, Satish Chandra Tiwari, Maneesha Gupta:
A closed-loop ASIC design approach based on logical effort theory and artificial neural networks. 10-22 - Ata Khorami, Roghayeh Saeidi, Manoj Sachdev, Mohammad Sharifkhani:
A low-power dynamic comparator for low-offset applications. 23-30 - Telajala Venkata Mahendra, Sheikh Wasmir Hussain, Sandeep Mishra, Anup Dandapat:
Low discharge precharge free matchline structure for energy-efficient search using CAM. 31-39
- Zhufei Chu, Lei Shi, Lun-Yao Wang, Yinshui Xia:
Multi-objective algebraic rewriting in XOR-majority graphs. 40-49
- Gereon Führ, Ahmed Hallawa, Rainer Leupers, Gerd Ascheid, Juan Fernando Eusse:
Multi-objective optimisation of software application mappings on heterogeneous MPSoCs: TONPET versus R2-EMOA. 50-61 - Chihiro Matsui, Ken Takeuchi:
Step-by-Step Design of memory hierarchy for heterogeneously-integrated SCM/NAND flash storage. 62-74
- Yiming Ouyang, Zhe Li, Jianhua Li, Chenglong Sun, Huaguo Liang, Gaoming Du:
CPCA: An efficient wireless routing algorithm in WiNoC for cross path congestion awareness. 75-84
- Nikolaos Kefalas, George Theodoridis:
Low-memory and high-performance architectures for the CCSDS 122.0-B-1 compression standard. 85-97 - Lennart Bamberg, Amir Najafi, Alberto García Ortiz:
Edge effect aware low-power crosstalk avoidance technique for 3D integration. 98-110 - Michail Noltsis, Eleni Maragkoudaki, Dimitrios Rodopoulos, Francky Catthoor, Dimitrios Soudris:
Failure probability of a FinFET-based SRAM cell utilizing the most probable failure point. 111-119 - Moritz Weißbrich, Lukas Gerlach, Holger Blume, Ardalan Najafi, Alberto García Ortiz, Guillermo Payá Vayá:
FLINT+: A runtime-configurable emulation-based stochastic timing analysis framework. 120-137 - Adrian Wheeldon, Jordan Morris, Danil Sokolov, Alex Yakovlev:
Self-timed, minimum latency circuits for the internet of things. 138-146
- Himadri Singh Raghav, Izzet Kale:
A balanced power analysis attack resilient adiabatic logic using single charge sharing transistor. 147-160 - Masanori Hashimoto, Kazutoshi Kobayashi, Jun Furuta, Shin-ichiro Abe, Yukinobu Watanabe:
Characterizing SRAM and FF soft error rates with measurement and simulation. 161-179 - Tohid Aghaei, Ali Naderi Saatlo:
A new strategy to design low power translinear based CMOS analog multiplier. 180-188 - Asieh Parhizkar Tarighat, Mostafa Yargholi:
Low power active shunt feedback CMOS low noise amplifier for wideband wireless systems. 189-197 - Seyyed Hasan Mozafari, Brett H. Meyer:
Characterizing the Effectiveness of Hot Sparing on Cost and Performance-per-Watt in Application Specific SIMT. 198-209 - Nguyen Van Toan, Dam Minh Tung, Jeong-Gun Lee:
A GALS design based on multi-frequency clocking for digital switching noise reduction. 210-224 - Stavroula Kapoulea, Costas Psychalinos, Ahmed S. Elwakil:
Realizations of simple fractional-order capacitor emulators with electronically-tunable capacitance. 225-233 - Huyen Pham Thi, Hanho Lee, Xuan Nghia Pham:
Half-row modified two-extra-column trellis min-max decoder architecture for nonbinary LDPC codes. 234-241 - Amitkumar S. Khade, Vibha S. Vyas, Mukul S. Sutaone:
Performance enhancement of advanced recycling folded cascode operational transconductance amplifier using an unbalanced biased input stage. 242-250 - Dengli Bu, Pengjun Wang:
An improved KFDD based reversible circuit synthesis method. 251-265 - Prathiba Ashok, Kanchana Bhaaskaran Vettuvanam Somasundaram:
Hardware footprints of S-box in lightweight symmetric block ciphers for IoT and CPS information security systems. 266-278 - M. Savitha, R. Venkat Siva Reddy:
Dual split-three segment capacitor array Design Based Successive approximation ADC for Io-T ecosystem. 279-288 - Dawei Li, Xiaowei Xu, Leibo Liu, Li Zhang, Cheng Zhuo, Yiyu Shi:
Optimal design of a low-power, phase-switching modulator for implantable medical applications. 289-300 - Baolin Wei, Tian Chen, Chao Lu, Weilin Xu, Yuanzhi Zhang, Xueming Wei, Hongwei Yue, Jihai Duan:
An all-digital frequency tunable IR-UWB transmitter with an approximate 15th derivative Gaussian pulse generator. 301-308 - Xin Feng, Youni Jiang, Xuejiao Yang, Ming Du, Xin Li:
Computer vision algorithms and hardware implementations: A survey. 309-320 - Hossein Sariri, Pooya Torkzadeh, Sirus Sadughi:
A novel design of hybrid-time-interleaved current steering digital to analog converter and its behavioral simulation considering non-ideal effects. 321-334 - Chase Cook, Hengyang Zhao, Takashi Sato, Masayuki Hiromoto, Sheldon X.-D. Tan:
GPU-based Ising computing for solving max-cut combinatorial optimization problems. 335-344 - Yuan Cheng, Chao Wang, Hai-Bao Chen, Hao Yu:
A large-scale in-memory computing for deep neural network with trained quantization. 345-355 - Xizi Chen, Jingbo Jiang, Jingyang Zhu, Chi-Ying Tsui:
SubMac: Exploiting the subword-based computation in RRAM-based CNN accelerator for energy saving and speedup. 356-368 - Maedeh Hemmat, Azadeh Davoodi:
Power-efficient ReRAM-aware CNN model generation. 369-380 - Manan Mewada, Mazad Zaveri, Rajesh Amratlal Thakker:
Improving the performance of transmission gate and hybrid CMOS Full Adders in chain and tree structure architectures. 381-392 - Haoyi Wang, Chenguang Wang, Yici Cai, Qiang Zhou:
A high-level information flow tracking method for detecting information leakage. 393-399
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