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ORCIDKazuteru Namba
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2020 – today
- 2024
[j43]Ji Wu, Ruoxi Yu, Kazuteru Namba:
6T-8T Hybrid SRAM for Lower-Power Neural-Network Processing by Lowering Operating Voltage. IEICE Trans. Inf. Syst. 107(9): 1278-1280 (2024)- [c37]Song Wang, Kazuteru Namba:
A Master-Slave Flip-Flop with Double-Node-Upset Self-Recovery and Soft Error Tolerance around Clock Edges. ICCE-Taiwan 2024: 1-2 - [c36]Kento Yano, You Yin, Kazuteru Namba:
Effect of RESET operation of CiM with PCM on recognition accuracy. ICCE-Taiwan 2024: 3-4 - [c35]Yoshiaki Saito, Kazuteru Namba, Josaphat Tetuko Sri Sumantyo:
Board design of digital chirp generator for earth observation. ICCE-Taiwan 2024: 61-62 - 2023
- [c34]Ji Wu, Kazuteru Namba:
SRAM-based efficiency memory model for quantized convolutional neural networks. ICCE-Taiwan 2023: 499-500 - 2022
- [j42]Keisuke Kozu, Yuya Tanabe, Masato Kitakami, Kazuteru Namba
:
Low Power Neural Network by Reducing SRAM Operating Voltage. IEEE Access 10: 116982-116986 (2022) - [c33]Shogo Takahashi, Kazuteru Namba:
A Double Node Upset tolerant SR latch using C-element. ICCE-TW 2022: 101-102 - [c32]Tomohiro Ishii, Kazuteru Namba:
Stuck-at Fault Tolerance in DNN Using Statistical data. PRDC 2022: 256-257 - 2021
- [c31]Keisuke Kozu, Kazuteru Namba:
Relaxing device requirements for non-linearity in Deep Neural Networks accelerators with Phase Change Memory. ICCE-TW 2021: 1-2 - 2020
- [j41]Kazuteru Namba:
Master-Slave FF Using DICE Capable of Tolerating Soft Errors Occurring Around Clock Edge. IEICE Trans. Inf. Syst. 103-D(4): 892-895 (2020) - [j40]Yuta Yamamoto, Kazuteru Namba:
Complete Double Node Upset Tolerant Latch Using C-Element. IEICE Trans. Inf. Syst. 103-D(10): 2125-2132 (2020) - [c30]Tomohiro Takahashi, Kazuteru Namba:
Influence of Recognition Performance on Recurrent Neural Network Using Phase-Change Memory as Synapses. ICCE-TW 2020: 1-2
2010 – 2019
- 2019
- [j39]Kazuteru Namba, Fabrizio Lombardi:
Coding for Write Latency Reduction in a Multi-Level Cell (MLC) Phase Change Memory (PCM). IEEE Trans. Computers 68(2): 301-306 (2019) - [c29]Shanshan Liu, Pedro Reviriego, Kazuteru Namba, Salvatore Pontarelli, Liyi Xiao, Fabrizio Lombardi:
Low Redundancy Double Error Correction Spotty Codes Combined with Gray Coding for 64 Data Bits Memories of 4-bit Multilevel Cells. DFT 2019: 1-4 - 2018
- [j38]Kazuteru Namba, Fabrizio Lombardi:
A Single and Adjacent Error Correction Code for Fast Decoding of Critical Bits. IEEE Trans. Computers 67(10): 1525-1531 (2018) - [j37]Kazuteru Namba, Fabrizio Lombardi:
On Coding for Endurance Enhancement and Error Control of Phase Change Memories With Write Latency Reduction. IEEE Trans. Very Large Scale Integr. Syst. 26(2): 230-238 (2018) - [c28]Yuta Yamamoto, Kazuteru Namba:
Construction of Latch Design with Complete Double Node Upset Tolerant Capability Using C-Element. DFT 2018: 1-6 - 2017
- [c27]Josaphat Tetuko Sri Sumantyo, Nobuyoshi Imura, Shunsuke Onishi, Tetsuo Yasaka, Robertus Heru Triharjanto, Koichi Ito, Steven Gao, Kazuteru Namba, Katsumi Hattori, Fumio Yamazaki, Chiharu Hongo, Akira Kato, Daniele Perissin:
L band circularly polarized SAR onboard microsatellite. IGARSS 2017: 5382-5385 - 2016
- [j36]Ri Cui, Kazuteru Namba:
A Calibration Technique for DVMC with Delay Time Controllable Inverter. IPSJ Trans. Syst. LSI Des. Methodol. 9: 30-36 (2016) - [j35]Wei Wei, Kazuteru Namba, Yong-Bin Kim, Fabrizio Lombardi:
A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories. IEEE Trans. Computers 65(3): 781-790 (2016) - [j34]Kazuteru Namba, Fabrizio Lombardi:
Single Multiscale-Symbol Error Correction Codes for Multiscale Storage Systems. IEEE Trans. Computers 65(6): 2005-2009 (2016) - [j33]Kazuteru Namba, Fabrizio Lombardi:
Parallel Decodable Multi-Level Unequal Burst Error Correcting Codes for Memories of Approximate Systems. IEEE Trans. Computers 65(12): 3794-3801 (2016) - [j32]Kazuteru Namba, Fabrizio Lombardi:
A Coding Scheme for Write Time Improvement of Phase Change Memory (PCM) Systems. IEEE Trans. Multi Scale Comput. Syst. 2(4): 291-296 (2016) - [c26]Hiroki Ueno, Kazuteru Namba:
Construction of a soft error (SEU) hardened Latch with high critical charge. DFT 2016: 27-30 - [c25]Wei Wei, Kazuteru Namba, Fabrizio Lombardi:
Design and Comparative Evaluation of a Hybrid Cache Memory at Architectural Level. ACM Great Lakes Symposium on VLSI 2016: 125-128 - 2015
- [j31]Kazuteru Namba, Fabrizio Lombardi:
Non-Binary Orthogonal Latin Square Codes for a Multilevel Phase Charge Memory (PCM). IEEE Trans. Computers 64(7): 2092-2097 (2015) - [j30]Kazuteru Namba, Fabrizio Lombardi:
Parallel Decodable Two-Level Unequal Burst Error Correcting Codes. IEEE Trans. Computers 64(10): 2902-2911 (2015) - [c24]Fabrizio Lombardi, Wei Wei, Kazuteru Namba:
Novel Designs of Embedded Hybrid Cells for High Performance Memory Circuits. ACM Great Lakes Symposium on VLSI 2015: 91-94 - [c23]Kentaroh Katoh, Kazuteru Namba:
A low area calibration technique of TDC using variable clock generator for accurate on-line delay measurement. ISQED 2015: 430-434 - 2014
- [j29]Wenpo Zhang, Kazuteru Namba, Hideo Ito:
Scan Shift Time Reduction Using Test Compaction for On-Chip Delay Measurement. IEICE Trans. Inf. Syst. 97-D(3): 533-540 (2014) - [j28]Wenpo Zhang, Kazuteru Namba, Hideo Ito:
Improving Small-Delay Fault Coverage of On-Chip Delay Measurement by Segmented Scan and Test Point Insertion. IEICE Trans. Inf. Syst. 97-D(10): 2719-2729 (2014) - [c22]Wei Wei, Fabrizio Lombardi, Kazuteru Namba:
Designs and analysis of non-volatile memory cells for single event upset (SEU) tolerance. DFT 2014: 69-74 - [c21]Wei Wei, Kazuteru Namba, Fabrizio Lombardi:
New 4T-based DRAM cell designs. ACM Great Lakes Symposium on VLSI 2014: 199-204 - 2013
- [j27]Wei Wei, Kazuteru Namba, Fabrizio Lombardi:
Extending Non-Volatile Operation to DRAM Cells. IEEE Access 1: 758-769 (2013) - [j26]Kazuteru Namba, Takashi Katagiri, Hideo Ito:
Timing-Error-Detecting Dual-Edge-Triggered Flip-Flop. J. Electron. Test. 29(4): 545-554 (2013) - [j25]Wenpo Zhang, Kazuteru Namba, Hideo Ito:
Improving Test Coverage by Measuring Path Delay Time Including Transmission Time of FF. IEICE Trans. Inf. Syst. 96-D(5): 1219-1222 (2013) - [j24]Kazuteru Namba, Nobuhide Takashina, Hideo Ito:
Design for Delay Measurement Aimed at Detecting Small Delay Defects on Global Routing Resources in FPGA. IEICE Trans. Inf. Syst. 96-D(8): 1613-1623 (2013) - [c20]Kazuteru Namba, Fabrizio Lombardi:
A novel scheme for concurrent error detection of OLS parallel decoders. DFTS 2013: 52-57 - [c19]Kouta Maebashi, Kazuteru Namba, Masato Kitakami:
Testing of switch blocks in TSV-reduced Three-Dimensional FPGA. DFTS 2013: 302-307 - 2012
- [j23]Kentaroh Katoh, Kazuteru Namba, Hideo Ito:
An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection. IEEE Trans. Very Large Scale Integr. Syst. 20(5): 804-817 (2012) - [c18]Takieddine Sbiai, Kazuteru Namba:
NoC Dynamically Reconfigurable as TAM. Asian Test Symposium 2012: 326-331 - [c17]Kazuteru Namba, Takashi Katagiri, Hideo Ito:
Dual-edge-triggered FF with timing error detection capability. DFT 2012: 187-192 - [c16]Wenpo Zhang, Kazuteru Namba, Hideo Ito:
Improving small-delay fault coverage for on-chip delay measurement. DFT 2012: 193-198 - 2011
- [j22]Kazuteru Namba, Hideo Ito:
Construction of BILBO FF with Soft-Error-Tolerant Capability. IEICE Trans. Inf. Syst. 94-D(5): 1045-1050 (2011) - [j21]Kiyonori Matsumoto, Kazuteru Namba, Hideo Ito:
Scan FF Reordering for Test Volume Reduction in Chiba-scan Architecture. IPSJ Trans. Syst. LSI Des. Methodol. 4: 140-149 (2011) - [j20]Kazuteru Namba, Hideo Ito:
Test Sets for Robust Path Delay Fault Testing on Two-Rail Logic Circuits. IEEE Trans. Computers 60(10): 1459-1470 (2011) - 2010
- [j19]Kazuteru Namba, Hideo Ito:
Chiba Scan Delay Fault Testing with Short Test Application Time. J. Electron. Test. 26(6): 667-677 (2010) - [j18]Kazuteru Namba, Kengo Nakashima, Hideo Ito:
Single-Event-Upset Tolerant RS Flip-Flop with Small Area. IEICE Trans. Inf. Syst. 93-D(12): 3407-3409 (2010) - [j17]Kazuteru Namba, Takashi Ikeda, Hideo Ito:
Construction of SEU Tolerant Flip-Flops Allowing Enhanced Scan Delay Fault Testing. IEEE Trans. Very Large Scale Integr. Syst. 18(9): 1265-1276 (2010) - [c15]Kentaroh Katoh, Kazuteru Namba, Hideo Ito:
A Low Area On-chip Delay Measurement System Using Embedded Delay Measurement Circuit. Asian Test Symposium 2010: 343-348 - [c14]Kazuteru Namba, Hideo Ito:
Soft Error Tolerant BILBO FF. DFT 2010: 73-81 - [c13]Kazuteru Namba, Masatoshi Sakata, Hideo Ito:
Single Event Induced Double Node Upset Tolerant Latch. DFT 2010: 280-288 - [c12]Masato Kitakami, Hiroshi Konno, Kazuteru Namba, Hideo Ito:
Quantitative Evaluation of Integrity for Remote System Using the Internet. PRDC 2010: 229-230
2000 – 2009
- 2009
- [j16]Kazuteru Namba, Yoshikazu Matsui, Hideo Ito:
Test Compression for IP Core Testing with Reconfigurable Network and Fixing-Flipping Coding. J. Electron. Test. 25(1): 97-105 (2009) - [j15]Kazuteru Namba, Hideo Ito:
Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding. IEICE Trans. Inf. Syst. 92-D(2): 269-282 (2009) - [j14]Kentaroh Katoh, Kazuteru Namba, Hideo Ito:
Design for Delay Fault Testability of 2-Rail Logic Circuits. IEICE Trans. Inf. Syst. 92-D(2): 336-341 (2009) - [j13]Kentaroh Katoh, Kazuteru Namba, Hideo Ito:
Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths. IEICE Trans. Inf. Syst. 92-D(3): 433-442 (2009) - [j12]Shuangyu Ruan, Kazuteru Namba, Hideo Ito:
Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability. IEICE Trans. Inf. Syst. 92-D(8): 1534-1541 (2009) - [j11]Kazuteru Namba, Hideo Ito:
Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(9): 2295-2303 (2009) - [c11]Kentaroh Katoh, Toru Tanabe, Haque Md Zahidul, Kazuteru Namba, Hideo Ito:
A Delay Measurement Technique Using Signature Registers. Asian Test Symposium 2009: 157-162 - [c10]Takumi Hoshi, Kazuteru Namba, Hideo Ito:
Testing of Switch Blocks in Three-Dimensional FPGA. DFT 2009: 227-235 - [c9]Masato Kitakami, Akihiro Katada, Kazuteru Namba, Hideo Ito:
Dependability Evaluation for Internet-Based Remote Systems. PRDC 2009: 256-259 - 2008
- [j10]Yoichi Sasaki, Kazuteru Namba, Hideo Ito:
Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger. J. Electron. Test. 24(1-3): 11-19 (2008) - [j9]Kentaroh Katoh, Kazuteru Namba, Hideo Ito:
Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability. Inf. Media Technol. 3(4): 704-716 (2008) - [j8]Kentaroh Katoh, Kazuteru Namba, Hideo Ito:
Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability. IPSJ Trans. Syst. LSI Des. Methodol. 1: 91-103 (2008) - [c8]Shuangyu Ruan, Kazuteru Namba, Hideo Ito:
Soft Error Hardened FF Capable of Detecting Wide Error Pulse. DFT 2008: 272-280 - [c7]Kazuteru Namba, Hideo Ito:
Delay Fault Testability on Two-Rail Logic Circuits. DFT 2008: 482-490 - [c6]Kazuteru Namba, Hideo Ito:
Path Delay Fault Test Set for Two-Rail Logic Circuits. PRDC 2008: 347-348 - 2007
- [j7]Kazuteru Namba, Eiji Fujiwara:
Nonbinary single-symbol error correcting, adjacent two-symbol transposition error correcting codes over integer rings. Syst. Comput. Jpn. 38(8): 54-60 (2007) - [c5]Takashi Ikeda, Kazuteru Namba, Hideo Ito:
Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing. DFT 2007: 282-290 - 2006
- [j6]Kazuteru Namba, Hideo Ito:
Proposal of Testable Multi-Context FPGA Architecture. IEICE Trans. Inf. Syst. 89-D(5): 1687-1693 (2006) - [j5]Kazuteru Namba, Hideo Ito:
Redundant Design for Wallace Multiplier. IEICE Trans. Inf. Syst. 89-D(9): 2512-2524 (2006) - [c4]Kazuteru Namba, Hideo Ito:
Interleaving of Delay Fault Tes Data for Efficient Test Compression with Statistical Coding. ATS 2006: 389-394 - [c3]Yoichi Sasaki, Kazuteru Namba, Hideo Ito:
Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit. DFT 2006: 327-335 - 2005
- [j4]Kazuteru Namba, Hideo Ito:
Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation. IEICE Trans. Inf. Syst. 88-D(9): 2135-2142 (2005) - [j3]Kazuteru Namba, Hideo Ito:
Scan Design for Two-Pattern Test without Extra Latches. IEICE Trans. Inf. Syst. 88-D(12): 2777-2785 (2005) - [c2]Kazuteru Namba, Hideo Ito:
Design of Defect Tolerant Wallace Multiplier. PRDC 2005: 300-304 - 2002
- [j2]Kazuteru Namba, Eiji Fujiwara:
Two-Level Unequal Error Protection Codes with Burst and Bit Error Correcting Capabilities. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(6): 1426-1430 (2002) - 2001
- [j1]Kazuteru Namba, Eiji Fujiwara:
A class of systematic m-ary single-symbol error correcting codes. Syst. Comput. Jpn. 32(6): 21-28 (2001) - [c1]Kazuteru Namba, Eiji Fujiwara:
Unequal Error Protection Codes with Two-Level Burst and Bit Error Correcting Capabilities. DFT 2001: 299-307
Coauthor Index
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