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ORCIDIEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 18
Volume 18, Number 1, January 2010
- Alireza Ejlali
, Bashir M. Al-Hashimi, Paul M. Rosinger, Seyed Ghassem Miremadi, Luca Benini:
Performability/Energy Tradeoff in Error-Control Schemes for On-Chip Networks. 1-14 - Yoonjin Kim, Rabi N. Mahapatra:
Dynamic Context Compression for Low-Power Coarse-Grained Reconfigurable Architecture. 15-28 - Venkataraman Mahalingam, Koustav Bhattacharya, N. Ranganathan, Hari Chakravarthula, Robin R. Murphy, Kevin S. Pratt:
A VLSI Architecture and Algorithm for Lucas-Kanade-Based Optical Flow Computation. 29-38 - Tsung-Han Tsai, Yu-Hsuan Lee, Yu-Yu Lee:
Design and Analysis of High-Throughput Lossless Image Compression Engine Using VLSI-Oriented FELICS Algorithm. 39-52 - Patrick Ndai, Nauman Rafique, Mithuna Thottethodi, Swaroop Ghosh, Swarup Bhunia, Kaushik Roy:
Trifecta: A Nonspeculative Scheme to Exploit Common, Data-Dependent Subcritical Paths. 53-65 - Wei Xu, Tong Zhang, Yiran Chen:
Design of Spin-Torque Transfer Magnetoresistive RAM and CAM/TCAM with High Sensing and Search Speed. 66-74 - Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy:
Self-Repairing SRAM Using On-Chip Detection and Compensation. 75-84 - Daesun Oh, Keshab K. Parhi:
Low-Complexity Switch Network for Reconfigurable LDPC Decoders. 85-94 - Andy Gean Ye:
Using the Minimum Set of Input Combinations to Minimize the Area of Local Routing Networks in Logic Clusters Containing Logically Equivalent I/Os in FPGAs. 95-107 - Yiyu Shi, Lei He:
EMPIRE: An Efficient and Compact Multiple-Parameterized Model-Order Reduction Method for Physical Optimization. 108-118 - Sheng-Guo Wang, Ben Wang:
Modeling of Distributed RLC Interconnect and Transmission Line via Closed Forms and Recursive Algorithms. 119-130 - Ganesh Venkataraman, Zhuo Feng, Jiang Hu, Peng Li:
Combinatorial Algorithms for Fast Clock Mesh Optimization. 131-141 - Ioannis Voyiatzis, Dimitris Gizopoulos, Antonis M. Paschalis:
Recursive Pseudo-Exhaustive Two-Pattern Generation. 142-152 - Yin Shen, Qiang Zhou, Yici Cai, Xianlong Hong:
ECP- and CMP-Aware Detailed Routing Algorithm for DFM. 153-157 - Eric Bohannon, Christopher Urban, Mark Pude, Yoshinori Nishi, Anand Gopalan, Ponnathpur R. Mukund:
Passive and Active Reduction Techniques for On-Chip High-Frequency Digital Power Supply Noise. 157-161 - Jacek Izydorczyk:
Three Steps to the Thermal Noise Death of Moore's Law. 161-165 - Harmander Singh, Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown:
Dynamically Pulsed MTCMOS With Bus Encoding for Reduction of Total Power and Crosstalk Noise. 166-170
Volume 18, Number 2, February 2010
- Wenping Wang, Shengqi Yang, Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Frank Liu, Yu Cao:
The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis. 173-183 - Shyue-Kung Lu, Chun-Lin Yang, Yuang-Cheng Hsiao, Cheng-Wen Wu:
Efficient BISR Techniques for Embedded Memories Considering Cluster Faults. 184-193 - Sleiman Bou-Sleiman, Jad G. Atallah, Saul Rodriguez, Ana Rusu, Mohammed Ismail:
Optimal Sigma Delta Modulator Architectures for Fractional- N Frequency Synthesis. 194-200 - Young-Ho Seo, Dong-Wook Kim:
A New VLSI Architecture of Parallel Multiplier-Accumulator Based on Radix-2 Modified Booth Algorithm. 201-208 - Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil D. Dutt:
CAPPS: A Framework for Power-Performance Tradeoffs in Bus-Matrix-Based On-Chip Communication Architecture Synthesis. 209-221 - Omid Sarbishei, Mohammad Maymandi-Nejad:
A Novel Overlap-Based Logic Cell: An Efficient Implementation of Flip-Flops With Embedded Logic. 222-231 - Matteo Agostinelli, Massimo Alioto, David Esseni, Luca Selmi:
Leakage-Delay Tradeoff in FinFET Logic Circuits: A Comparative Analysis With Bulk Technology. 232-245 - Da-Cheng Juan, Yu-Ting Chen, Ming-Chao Lee, Shih-Chieh Chang:
An Efficient Wake-Up Strategy Considering Spurious Glitches Phenomenon for Power Gating Designs. 246-255 - Víctor H. Champac, Victor Avendaño, Joan Figueras:
Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals. 256-269 - Kunhyuk Kang, Sang Phill Park, Keejong Kim, Kaushik Roy:
On-Chip Variability Sensor Using Phase-Locked Loop for Detecting and Correcting Parametric Timing Failures. 270-280 - Myeong-Eun Hwang, Kaushik Roy:
ABRM: Adaptive Beta -Ratio Modulation for Process-Tolerant Ultradynamic Voltage Scaling. 281-290 - Yuan-Hao Huang:
High-Efficiency Soft-Error-Tolerant Digital Signal Processing Using Fine-Grain Subword-Detection Processing. 291-304 - Donghoon Han, Byung-Sung Kim, Abhijit Chatterjee:
DSP-Driven Self-Tuning of RF Circuits for Process-Induced Performance Variability. 305-314 - Jigang Wu, Thambipillai Srikanthan, Xiaogang Han:
Preprocessing and Partial Rerouting Techniques for Accelerating Reconfiguration of Degradable VLSI Arrays. 315-319 - Chun-Lung Hsu, Chang-Hsin Cheng, Yu Liu:
Built-in Self-Detection/Correction Architecture for Motion Estimation Computing Arrays. 319-324 - Maoxiang Yi, Huaguo Liang, Lei Zhang, Wenfa Zhan:
A Novel x -ploiting Strategy for Improving Performance of Test Data Compression. 324-329 - Giorgio Di Natale, M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre:
Self-Test Techniques for Crypto-Devices. 329-333 - Irith Pomeranz, Sudhakar M. Reddy:
Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Scan-Based Tests. 333-337 - Abinash Roy, Jingye Xu, Masud H. Chowdhury:
Analysis of the Impacts of Signal Slew and Skew on the Behavior of Coupled RLC Interconnects for Different Switching Patterns. 338-342
Volume 18, Number 3, March 2010
- Niraj K. Jha:
Editorial: New Associate Editor Appointments. 345-346 - Sherif A. Tawfik, Volkan Kursun:
Dual Supply Voltages and Dual Clock Frequencies for Lower Clock Power and Suppressed Temperature-Gradient-Induced Clock Skew. 347-355 - Mohamed H. Abu-Rahma, Mohab Anis, Sei Seung Yoon:
Reducing SRAM Power Using Fine-Grained Wordline Pulsewidth Control. 356-364 - Elham Safi, Andreas Moshovos, Andreas G. Veneris:
On the Latency and Energy of Checkpointed Superscalar Register Alias Tables. 365-377 - Arthur Nieuwoudt, Jamil Kawa, Yehia Massoud:
Crosstalk-Induced Delay, Noise, and Interconnect Planarization Implications of Fill Metal in Nanoscale Process Technology. 378-391 - Wei-Chung Kao, Wei-Shun Chuang, Shiu-Ting Lin, Chien-Mo James Li, Vasco Manquinho:
DFT and Minimum Leakage Pattern Generation for Static Power Reduction During Test and Burn-In. 392-400 - Irith Pomeranz, Sudhakar M. Reddy:
Path Selection for Transition Path Delay Faults. 401-409 - Weidong Kuang, Peiyi Zhao, Jiann-Shiun Yuan, Ronald F. DeMara:
Design of Asynchronous Circuits for High Soft Error Tolerance in Deep Submicrometer CMOS Circuits. 410-422 - Akhilesh Kumar, Mohab Anis:
FPGA Design for Timing Yield Under Process Variations. 423-435 - Christos-Savvas Bouganis, Iosifina Pournara, Peter Y. K. Cheung:
Exploration of Heterogeneous FPGAs for Mapping Linear Projection Designs. 436-449 - Syed M. Alam, Robert E. Jones, Scott Pozder, Ritwik Chatterjee, Shahid Rauf, Ankur Jain:
Interstratum Connection Design Considerations for Cost-Effective 3-D System Integration. 450-460 - Zhenghao Lu, Kiat Seng Yeo, Wei Meng Lim, Manh Anh Do, Chirn Chye Boon:
Design of a CMOS Broadband Transimpedance Amplifier With Active Feedback. 461-472 - Pei-Yin Chen, Chih-Yuan Lien, Hsu-Ming Chuang:
A Low-Cost VLSI Implementation for Efficient Removal of Impulse Noise. 473-481 - Naoya Onizawa, Takahiro Hanyu, Vincent C. Gaudet:
Design of High-Throughput Fully Parallel LDPC Decoders Based on Wire Partitioning. 482-489 - Milin Zhang, Amine Bermak:
Compressive Acquisition CMOS Image Sensor: From the Algorithm to Hardware Implementation. 490-500 - Meikang Qiu, Laurence Tianruo Yang, Zili Shao, Edwin Hsing-Mean Sha:
Dynamic and Leakage Energy Minimization With Soft Real-Time Loop Scheduling and Voltage Assignment. 501-504 - Hyung-Ock Kim, Bong Hyun Lee, Jong-Tae Kim, Jung Yun Choi, Kyu-Myung Choi, Youngsoo Shin:
Supply Switching With Ground Collapse for Low-Leakage Register Files in 65-nm CMOS. 505-509 - Ying-Zu Lin, Cheng-Wu Lin, Soon-Jyh Chang:
A 5-bit 3.2-GS/s Flash ADC With a Digital Offset Calibration Scheme. 509-513
Volume 18, Number 4, April 2010
- Yang Liu, Tong Zhang, Keshab K. Parhi:
Computation Error Analysis in Digital Signal Processing Systems With Overscaled Supply Voltage. 517-526 - Teijo Lehtonen, David Wolpert, Pasi Liljeberg, Juha Plosila, Paul Ampadu:
Self-Adaptive System for Addressing Permanent Errors in On-Chip Interconnects. 527-540 - Mao-Yin Wang, Chih-Pin Su, Chia-Lung Horng, Cheng-Wen Wu, Chih-Tsun Huang:
Single- and Multi-core Configurable AES Architectures for Flexible Security. 541-552 - Chen-Hsing Wang, Chieh-Lin Chuang, Cheng-Wen Wu:
An Efficient Multimode Multiplier Supporting AES and Fundamental Operations of Public-Key Cryptosystems. 553-563 - Deming Chen, Jason Cong, Yiping Fan, Lu Wan:
LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization. 564-577 - Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Improving FPGA Performance for Carry-Save Arithmetic. 578-590 - Aristides Efthymiou:
Initialization-Based Test Pattern Generation for Asynchronous Circuits. 591-601 - Wook Kim, Kyung Tae Do, Young Hwan Kim:
Statistical Leakage Estimation Based on Sequential Addition of Cell Leakage Currents. 602-615 - Guillermo Botella Juan, Antonio García Ríos, M. Rodriguez-Alvarez, Eduardo Ros Vidal, Uwe Meyer-Bäse, María C. Molina:
Robust Bioinspired Architecture for Optical-Flow Computation. 616-629 - Min Ni, Seda Ogrenci Memik:
A Fast Heuristic Algorithm for Multidomain Clock Skew Scheduling. 630-637 - S. M. Rezaul Hasan:
Analysis and Design of a Multistage CMOS Band-Pass Low-Noise Preamplifier for Ultrawideband RF Receiver. 638-651 - Mohammad Taherzadeh-Sani, Anas A. Hamoui:
Area and Power Optimization of High-Order Gain Calibration in Digitally-Enhanced Pipelined ADCs. 652-657 - Rajsekhar Adapa, Spyros Tragoudas:
Techniques to Prioritize Paths for Diagnosis. 658-661 - Chao-Yang Kao, Cheng-Long Wu, Youn-Long Lin:
A High-Performance Three-Engine Architecture for H.264/AVC Fractional Motion Estimation. 662-666 - Ritu Singhal, Asha Balijepalli, Anupama R. Subramaniam, Chi-Chao Wang, Frank Liu, Sani R. Nassif, Yu Cao:
Modeling and Analysis of the Nonrectangular Gate Effect for Postlithography Circuit Simulation. 666-670 - Rahul Kalra, Roman L. Lysecky:
Configuration Locking and Schedulability Estimation for Reduced Reconfiguration Overheads of Reconfigurable Systems. 671-674 - Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh:
Post-Manufacture Tuning for Nano-CMOS Yield Recovery Using Reconfigurable Logic. 675-679 - Luca P. Carloni, Andrew B. Kahng, Sudhakar Muddu, Alessandro Pinto, Kambiz Samadi, Puneet Sharma:
Accurate Predictive Interconnect Modeling for System-Level Design. 679-684 - Song Liu, Yu Zhang, Seda Ogrenci Memik, Gokhan Memik:
An Approach for Adaptive DRAM Temperature and Power Management. 684-688
Volume 18, Number 5, May 2010
- Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny:
Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect. 689-696 - Massimo Alioto, Gaetano Palumbo, Melita Pennisi:
Understanding the Effect of Process Variations on the Delay of Static and Domino Logic. 697-710 - Massimo Alioto, Massimo Poli, Santina Rocchi:
A General Power Model of Differential Power Analysis Attacks to Static Logic Circuits. 711-724 - Mao-Yin Wang, Cheng-Wen Wu:
A Mesh-Structured Scalable IPsec Processor. 725-731 - Fu-Ching Yang, Cheng-Lung Chiang, Ing-Jer Huang:
A Reverse-Encoding-Based On-Chip Bus Tracer for Efficient Circular-Buffer Utilization. 732-741 - Renatas Jakushokas, Eby G. Friedman:
Resource Based Optimization for Simultaneous Shield and Repeater Insertion. 742-749 - Zhiyi Yu, Bevan M. Baas:
A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors. 750-762 - Hiroyuki Yamauchi:
A Discussion on SRAM Circuit Design Trend in Deeper Nanometer-Scale Technologies. 763-774 - Ali Namazi, Mehrdad Nourani:
Gate-Level Redundancy: A New Design-for-Reliability Paradigm for Nanotechnologies. 775-786 - Jongsun Park, Jung Hwan Choi, Kaushik Roy:
Dynamic Bit-Width Adaptation in DCT: An Approach to Trade Off Image Quality and Computation Energy. 787-793 - Irfan Habib, Özgün Paker, Sergei Sawitzki:
Design Space Exploration of Hard-Decision Viterbi Decoding: Algorithm and VLSI Implementation. 794-807 - Jinjin He, Zhongfeng Wang, Huaping Liu:
An Efficient 4-D 8PSK TCM Decoder Architecture. 808-817 - Soo Yun Hwang, Dong-Soo Kang, Hyeong Jun Park, Kyoung Son Jhang:
Implementation of a Self-Motivated Arbitration Scheme for the Multilayer AHB Busmatrix. 818-830 - Asral Bahari, Tughrul Arslan, Ahmet T. Erdogan:
Interframe Bus Encoding Technique and Architecture for MPEG-4 AVC/H.264 Video Compression. 831-835 - Ruzica Jevtic, Carlos Carreras:
Power Estimation of Embedded Multiplier Blocks in FPGAs. 835-839 - Yun-Nan Chang:
A Multibank Memory-Based VLSI Architecture of DVB Symbol Deinterleaver. 840-843 - Hyojin Choi, Wei Liu, Wonyong Sung:
VLSI Implementation of BCH Error Correction for Multilevel Cell NAND Flash Memory. 843-847 - Somsubhra Talapatra, Hafizur Rahaman, Jimson Mathew:
Low Complexity Digit Serial Systolic Montgomery Multipliers for Special Class of GF(2m). 847-852 - Fadi J. Kurdahi, Ahmed M. Eltawil, Kang Yi, Stanley Cheng, Amin Khajeh:
Low-Power Multimedia System Design by Aggressive Voltage Scaling. 852-856
Volume 18, Number 6, June 2010
- Yat-Hei Lam, Wing-Hung Ki:
CMOS Bandgap References With Self-Biased Symmetrically Matched Current-Voltage Mirror and Extension of Sub-1-V Design. 857-865 - Chao-Yang Kao, Youn-Long Lin:
A Memory-Efficient and Highly Parallel Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC. 866-874 - Tae-Hwan Kim, Youngjoo Lee, In-Cheol Park:
Design of a Scalable and Programmable Sound Synthesizer. 875-886 - Andrew Carlson, Zheng Guo, Sriram Balasubramanian, Radu Zlatanovici, Tsu-Jae King Liu, Borivoje Nikolic:
SRAM Read/Write Margin Enhancements Using FinFETs. 887-900 - Erdem Serkan Erdogan, Sule Ozev:
Detailed Characterization of Transceiver Parameters Through Loop-Back-Based BiST. 901-911 - Jin-Fu Li:
Testing Comparison and Delay Faults of TCAMs With Asymmetric Cells. 912-920 - Tsu-Wei Tseng, Jin-Fu Li, Chih-Chiang Hsu:
ReBISR: A Reconfigurable Built-In Self-Repair Scheme for Random Access Memories in SOCs. 921-932 - Jerzy J. Dabrowski, Rashad Ramzan:
Built-in Loopback Test for IC RF Transceivers. 933-946 - John Keane, Tony Tae-Hyoung Kim, Chris H. Kim:
An On-Chip NBTI Sensor for Measuring pMOS Threshold Voltage Degradation. 947-956 - Tse-Wei Chen, Shao-Yi Chien:
Bandwidth Adaptive Hardware Architecture of K-Means Clustering for Video Analysis. 957-966 - Aamir Zia, Philip Jacob, Jin Woo Kim, Michael Chu, Russell P. Kraft, John F. McDonald:
A 3-D Cache With Ultra-Wide Data Bus for 3-D Processor-Memory Integration. 967-977 - Jing-Ling Yang:
Parallel Interleavers Through Optimized Memory Address Remapping. 978-987 - Aviral Shrivastava, Deepa Kannan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula:
Reducing Functional Unit Power Consumption and its Variation Using Leakage Sensors. 988-997 - Haralampos-G. D. Stratigopoulos, Petros Drineas, Mustapha Slamani, Yiorgos Makris:
RF Specification Test Compaction Using Learning Machines. 998-1002 - Shiyan Hu, Patrik Shah, Jiang Hu:
Pattern Sensitive Placement Perturbation for Manufacturability. 1002-1006 - Venkataraman Mahalingam, N. Ranganathan:
Timing-Based Placement Considering Uncertainty Due to Process Variations. 1007-1011 - Edward Flanigan, Spyros Tragoudas:
Identification of Delay Measurable PDFs Using Linear Dependency Relationships. 1011-1015 - Basel Halak, Alexandre Yakovlev:
Throughput Optimization for Area-Constrained Links With Crosstalk Avoidance Methods. 1016-1019 - Youngsun Han, Peter Harliman, Seon Wook Kim, Jong-Kook Kim, Chulwoo Kim:
A Novel Architecture for Block Interleaving Algorithm in MB-OFDM Using Mixed Radix System. 1020-1024
Volume 18, Number 7, July 2010
- Rupak Samanta, Jiang Hu, Peng Li:
Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks. 1025-1035 - You-Hsien Lin, Terng-Yin Hsu:
Low-Complexity All-Digital Sample Clock Dither for OFDM Timing Recovery. 1036-1042 - Montek Singh, José A. Tierno, Alexander V. Rylyakov, Sergey V. Rylov, Steven M. Nowick:
An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz. 1043-1056 - Gang Zhou, Harald Michalik, László Hinsenkamp:
Complexity Analysis and Efficient Implementations of Bit Parallel Finite Field Multipliers Based on Karatsuba-Ofman Algorithm on FPGAs. 1057-1066 - Faizal Arya Samman, Thomas Hollstein, Manfred Glesner:
Adaptive and Deadlock-Free Tree-Based Multicast Routing for Networks-on-Chip. 1067-1080 - Jia Li, Qiang Xu, Yu Hu, Xiaowei Li:
X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing. 1081-1092 - Sam Taylor, Doug A. Edwards, Luis A. Plana, Luis A. Tarazona:
Asynchronous Data-Driven Circuit Synthesis. 1093-1106 - Rostislav (Reuven) Dobkin, Michael Moyal, Avinoam Kolodny, Ran Ginosar:
Asynchronous Current Mode Serial Communication. 1107-1117 - Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye:
Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits. 1118-1129 - Sunghwa Ok, Kyunghoon Chung, Jabeom Koo, Chulwoo Kim:
An Antiharmonic, Programmable, DLL-Based Frequency Multiplier for Dynamic Frequency Scaling. 1130-1134 - Kuen-Jong Lee, Tong-Yu Hsieh, Chin-Yao Chang, Yu-Ting Hong, Wen-Cheng Huang:
On-Chip SOC Test Platform Design Based on IEEE 1500 Standard. 1134-1139 - Jaydeb Bhaumik, Dipanwita Roy Chowdhury:
New Architectural Design of CA-Based Codec. 1139-1144
Volume 18, Number 8, August 2010
- Jun-Hong Chen, Ming-Der Shieh, Wen-Ching Lin:
A High-Performance Unified-Field Reconfigurable Cryptographic Processor. 1145-1158 - Adam B. Kinsman, Nicola Nicolici:
Time-Multiplexed Compressed Test of SOC Designs. 1159-1172 - Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Variation-Aware System-Level Power Analysis. 1173-1184 - Jie Jin, Chi-Ying Tsui:
An Energy Efficient Layered Decoding Architecture for LDPC Decoder. 1185-1195 - Xi Chen, Lei Yang, Robert P. Dick, Li Shang, Haris Lekatsas:
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm. 1196-1208 - Patrick Ndai, Ashish Goel, Kaushik Roy:
A Scalable Circuit-Architecture Co-Design to Improve Memory Yield for High-Performance Processors. 1209-1219 - Chia-Yi Lin, Hsiu-Chuan Lin, Hung-Ming Chen:
On Reducing Test Power and Test Volume by Selective Pattern Compression Schemes. 1220-1224 - Ning Zhu, Wang Ling Goh, Weija Zhang, Kiat Seng Yeo, Zhi-Hui Kong:
Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing. 1225-1229 - Irith Pomeranz, Sudhakar M. Reddy:
Robust Fault Models Where Undetectable Faults Imply Logic Redundancy. 1230-1234 - Chiou-Yng Lee, Pramod Kumar Meher, Jagdish Chandra Patra:
Concurrent Error Detection in Bit-Serial Normal Basis Multiplication Over GF(2m) Using Multiple Parity Prediction Schemes. 1234-1238 - Kiichi Niitsu, Yoshinori Kohama, Yasufumi Sugimori, Kazutaka Kasuga, Kenichi Osada, Naohiko Irie, Hiroki Ishikuro, Tadahiro Kuroda:
Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration. 1238-1243 - Ahmed Youssef, Mohamed Zahran, Mohab Anis, Mohamed I. Elmasry:
On the Power Management of Simultaneous Multithreading Processors. 1243-1248 - Xuan Guan, Yunsi Fei:
Register File Partitioning and Compiler Support for Reducing Embedded Processor Power Consumption. 1248-1252 - Nicholas Allec, Robert G. Knobel, Li Shang:
An Adaptive Algorithm for Single-Electron Device and Circuit Simulation. 1253-1257 - Chenjie Yu, Peter Petrov:
Low-Cost and Energy-Efficient Distributed Synchronization for Embedded Multiprocessors. 1257-1261 - Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny:
Corrections to "Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect" [May 10 689-696]. 1262
Volume 18, Number 9, September 2010
- Kazuteru Namba, Takashi Ikeda, Hideo Ito:
Construction of SEU Tolerant Flip-Flops Allowing Enhanced Scan Delay Fault Testing. 1265-1276 - Kanad Basu, Prabhat Mishra:
Test Data Compression Using Efficient Bitmask and Dictionary Selection Methods. 1277-1286 - Kris Heyrman, Antonis Papanikolaou, Francky Catthoor, Peter Veelaert, Wilfried Philips:
Control for Power Gating of Wires. 1287-1300 - Swaroop Ghosh, Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy:
Voltage Scalable High-Speed Robust Hybrid Arithmetic Units Using Adaptive Clocking. 1301-1309 - Hyunseok Lee, Chaitali Chakrabarti, Trevor N. Mudge:
A Low-Power DSP for Wireless Communications. 1310-1322 - Jieyi Long, Ja Chun Ku, Seda Ogrenci Memik, Yehea I. Ismail:
SACTA: A Self-Adjusting Clock Tree Architecture for Adapting to Thermal-Induced Delay Variation. 1323-1336 - Alexander V. Mitev, Michael M. Marefat, Dongsheng Ma, Janet Meiling Wang:
Principle Hessian Direction-Based Parameter Reduction for Interconnect Networks With Process Variation. 1337-1347 - Erkan Acar, Sule Ozev:
Low Cost MIMO Testing for RF Integrated Circuits. 1348-1356 - Irith Pomeranz, Sudhakar M. Reddy:
Switching Activity as a Test Compaction Heuristic for Transition Faults. 1357-1361 - Jin-Fu Li, Tsu-Wei Tseng, Chih-Sheng Hou:
Reliability-Enhancement and Self-Repair Schemes for SRAMs With Static and Dynamic Faults. 1361-1366 - Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan:
Test Generation in Systolic Architecture for Multiplication Over GF(2 m). 1366-1371 - Venkata K. Kidambi Srinivasan, Chitranjan K. Singh, Poras T. Balsara:
A Generic Scalable Architecture for Min-Sum/Offset-Min-Sum Unit for Irregular/Regular LDPC Decoder. 1372-1376 - Sudeep Pasricha, Fadi J. Kurdahi, Nikil D. Dutt:
Evaluating Carbon Nanotube Global Interconnects for Chip Multiprocessor Applications. 1376-1380 - Neha V. Karanjkar, Rasmi R. Sahoo, Maryam Shojaei Baghini:
Comments on "Improved Accuracy Pseudo-Exponential Function Generator With Applications in Analog Signal Processing". 1381-1383
Volume 18, Number 10, October 2010
- Charles Thangaraj, Robert Pownall, Phil Nikkel, Guangwei Yuan, Kevin L. Lear, Tom Chen:
Fully CMOS-Compatible On-Chip Optical Clock Distribution and Recovery. 1385-1398 - Hao Yu, Chunta Chu, Yiyu Shi, David Smart, Lei He, Sheldon X.-D. Tan:
Fast Analysis of a Large-Scale Inductive Interconnect by Block-Structure-Preserved Macromodeling. 1399-1411 - Shu Li, Tong Zhang:
Improving Multi-Level NAND Flash Memory Storage Reliability Using Concatenated BCH-TCM Coding. 1412-1420 - Girish Varatkar, Shrikanth S. Narayanan, Naresh R. Shanbhag, Douglas L. Jones:
Stochastic Networked Computation. 1421-1432 - Ali Namazi, Mehrdad Nourani, M. Saquib:
A Fault-Tolerant Interconnect Mechanism for NMR Nanoarchitectures. 1433-1446 - Bo Xiang, Rui Shen, An Pan, Dan Bao, Xiaoyang Zeng:
An Area-Efficient and Low-Power Multirate Decoder for Quasi-Cyclic Low-Density Parity-Check Codes. 1447-1460 - Georgios Karakonstantis, Nilanjan Banerjee, Kaushik Roy:
Process-Variation Resilient and Voltage-Scalable DCT Architecture for Robust Low-Power Computing. 1461-1470 - Yoonjin Kim, Rabi N. Mahapatra, Kiyoung Choi:
Design Space Exploration for Efficient Resource Utilization in Coarse-Grained Reconfigurable Architecture. 1471-1482 - Jinkyu Lee, Nur A. Touba:
Correlation-Based Rectangular Encoding. 1483-1492 - Shiann-Rong Kuang, Jiun-Ping Wang, Hong-Yi Huang:
Variable-Latency Floating-Point Multipliers for Low-Power Applications. 1493-1497 - Sudip Mondal, Ahmed M. Eltawil, Chung-An Shen, Khaled N. Salama:
Design and Implementation of a Sort-Free K-Best Sphere Decoder. 1497-1501
Volume 18, Number 11, November 2010
- Sean O'Melia, Adam J. Elbirt:
Enhancing the Performance of Symmetric-Key Cryptography via Instruction Set Extensions. 1505-1518 - Hai Lin, Yunsi Fei, Xuan Guan, Zhijie Jerry Shi:
Architectural Enhancement and System Software Support for Program Code Integrity Monitoring in Application-Specific Instruction-Set Processors. 1519-1532 - Irith Pomeranz, Sudhakar M. Reddy:
Selection of a Fault Model for Fault Diagnosis Based on Unique Responses. 1533-1543 - Karim Mohammed, Babak Daneshrad:
A MIMO Decoder Accelerator for Next Generation Wireless Communications. 1544-1555 - Ruijing Shen, Sheldon X.-D. Tan, Jian Cui, Wenjian Yu, Yici Cai, Gengsheng Chen:
Variational Capacitance Extraction and Modeling Based on Orthogonal Polynomial Method. 1556-1566 - Hamed F. Dadgour, Kaustav Banerjee:
A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-In Dynamic or Gates. 1567-1577 - Soheil Ghiasi:
On Incremental Component Implementation Selection in System Synthesis. 1578-1589 - Gregory K. Chen, Dennis Sylvester, David T. Blaauw, Trevor N. Mudge:
Yield-Driven Near-Threshold SRAM Design. 1590-1598 - Yen-Jen Chang:
Don't-Care Gating (DCG) TCAM Design Used in Network Routing Table. 1599-1607 - Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino:
Temperature-Insensitive Dual- Vth Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence. 1608-1620 - Yiran Chen, Hai Li, Cheng-Kok Koh, Guangyu Sun, Jing Li, Yuan Xie, Kaushik Roy:
Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance. 1621-1624
Volume 18, Number 12, December 2010
- Giorgio Boselli, Gabriella Trucco, Valentino Liberali:
Properties of Digital Switching Currents in Fully CMOS Combinational Logic. 1625-1638 - Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu:
An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement. 1639-1648 - Vyas Krishnan, Srinivas Katkoori:
TABS: Temperature-Aware Layout-Driven Behavioral Synthesis. 1649-1659 - Maziar Goudarzi, Tohru Ishihara:
SRAM Leakage Reduction by Row/Column Redundancy Under Random Within-Die Delay Variation. 1660-1671 - Seongmoon Wang, Wenlong Wei, Zhanglei Wang:
A Low Overhead High Test Compression Technique Using Pattern Clustering With $n$-Detection Test Support. 1672-1685 - Hsien-Te Chen, Chieh-Chun Chang, TingTing Hwang:
Reconfigurable ECO Cells for Timing Closure and IR Drop Minimization. 1686-1695 - Peter A. Jamieson, Jonathan Rose:
Enhancing the Area Efficiency of FPGAs With Hard Circuits Using Shadow Clusters. 1696-1709 - Jing Li, Patrick Ndai, Ashish Goel, Sayeef S. Salahuddin, Kaushik Roy:
Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective. 1710-1723 - Yiran Chen, Xiaobin Wang, Hai Li, Haiwen Xi, Yuan Yan, Wenzhong Zhu:
Design Margin Exploration of Spin-Transfer Torque RAM (STT-RAM) in Scaled Technologies. 1724-1734 - Reza M. Rad, James F. Plusquellic, Mohammad Tehranipoor:
A Sensitivity Analysis of Power Signal Methods for Detecting Hardware Trojans Under Real Process and Environmental Conditions. 1735-1744 - Katsuhiko Hoya, Daisaburo Takashima, Shinichiro Shiratake, Ryu Ogiwara, Tadashi Miyakawa, Hidehiro Shiga, Sumiko M. Doumae, Sumito Ohtsuki, Yoshinori Kumura, Susumu Shuto, Tohru Ozaki, Koji Yamakawa, Iwao Kunishima, Akihiro Nitayama, Shuso Fujii:
A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode. 1745-1752 - Tim Good, Mohammed Benaissa:
692-nW Advanced Encryption Standard (AES) on a 0.13-mum CMOS. 1753-1757 - Ka Nang Leung, Yuan Yen Mai, Philip K. T. Mok:
A Chip-Area Efficient Voltage Regulator for VLSI Systems. 1757-1762 - Chin-Lung Su, Chih-Wea Tsai, Ching-Yi Chen, Wan-Yu Lo, Cheng-Wen Wu, Ji-Jan Chen, Wen Ching Wu, Chien-Chung Hung, Ming-Jer Kao:
Diagnosis of MRAM Write Disturbance Fault. 1762-1766 - Chip-Hong Chang, Ravi Kumar Satzoda:
A Low Error and High Performance Multiplexer-Based Truncated Multiplier. 1767-1771
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