default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDRégis Leveugle
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
[c123]Sami El Amraoui
, Régis Leveugle, Paolo Maistri:
Choose your Path: Control of Ring Oscillators EMFI Susceptibility through FPGA P&R Constraints. DDECS 2024: 118-123- [c122]Sami El Amraoui, Aghiles Douadi, Régis Leveugle, Paolo Maistri:
Harmonic Response of Ring Oscillators under Single ElectroMagnetic Pulsed Fault Injection. LATS 2024: 1-6 - [c121]Régis Leveugle, Nathan Hocquette, Charles Labarre, Romain Plumaugat, Loic Tcharoukian, Valentin Martinoli, Yannick Teglia:
Secured Bus as a Countermeasure against Covert Channels: NEORV32 Case Study. LATS 2024: 1-2 - 2022
- [c120]Valentin Martinoli, Yannick Teglia, Abdellah Bouagoun, Régis Leveugle:
Recovering Information on the CVA6 RISC-V CPU with a Baremetal Micro-Architectural Covert Channel. IOLTS 2022: 1-6 - [c119]Luc Noizette, Florent Miller, Thierry Colladant, Youri Helen, Régis Leveugle:
Using Application Profiling based on a Virtual Platform for SoC Fault Tolerance Assessment. PRIME 2022: 225-228 - [i1]Valentin Martinoli, Yannick Teglia, Abdellah Bouagoun, Régis Leveugle:
CVA6's Data cache: Structure and Behavior. CoRR abs/2202.03749 (2022) - 2021
- [c118]Michele Portolan, Vincent Reynaud, Paolo Maistri, Régis Leveugle, Giorgio Di Natale:
Security EDA Extension through P1687.1 and 1687 Callbacks. ITC 2021: 344-353 - [c117]Paolo Maistri, Vincent Reynaud, Michele Portolan, Régis Leveugle:
Secure Test with RSNs: Seamless Authenticated Extended Confidentiality. NEWCAS 2021: 1-4 - [c116]Julie Roux, Katell Morin-Allory, Vincent Beroulle, Régis Leveugle, Lilian Bossuet, Frédéric Cézilly, Frédéric Berthoz, Gilles Genévrier, François Cerisier:
Cross-layer Approach to Assess FMEA on Critical Systems and Evaluate High-Level Model Realism. VLSI-SoC 2021: 1-6 - [c115]Julie Roux, Katell Morin-Allory, Vincent Beroulle, Lilian Bossuet, Frédéric Cézilly, Frédéric Berthoz, Gilles Genévrier, François Cerisier, Régis Leveugle:
FMEA on Critical Systems: A Cross-Layer Approach Based on High-Level Models. VLSI-SoC (Selected Papers) 2021: 113-133 - 2020
- [c114]Julie Roux, Vincent Beroulle, Katell Morin-Allory, Régis Leveugle, Lilian Bossuet, Frédéric Cézilly, Frédéric Berthoz, Gilles Genévrier, François Cerisier:
Cross Layer Fault Simulations for Analyzing the Robustness of RTL Designs in Airborne Systems. DDECS 2020: 1-4 - [c113]Michele Portolan, Vincent Reynaud, Paolo Maistri, Régis Leveugle:
Dynamic Authentication-Based Secure Access to Test Infrastructure. ETS 2020: 1-6 - [c112]Julie Roux, Vincent Beroulle, Katell Morin-Allory, Régis Leveugle, Lilian Bossuet, Frédéric Cézilly, Frédéric Berthoz, Gilles Genévrier, François Cerisier:
High Level Fault Injection Method for Evaluating Critical System Parameter Ranges. ICECS 2020: 1-4 - [c111]Michele Portolan, R. Silveira Feitoza, Ghislain Takam Tchendjou, Vincent Reynaud, Kalpana Senthamarai Kannan, Manuel J. Barragán, Emmanuel Simeu, Paolo Maistri, Lorena Anghel, Régis Leveugle, Salvador Mir:
A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System. IOLTS 2020: 1-4
2010 – 2019
- 2019
- [c110]Michele Portolan, Alessandro Savino, Régis Leveugle, Stefano Di Carlo, Alberto Bosio, Giorgio Di Natale:
Alternatives to Fault Injections for Early Safety/Security Evaluations. ETS 2019: 1-10 - [c109]Alessandro Savino, Michele Portolan, Régis Leveugle, Stefano Di Carlo:
Approximate computing design exploration through data lifetime metrics. ETS 2019: 1-7 - [c108]Marc Merandat, Vincent Reynaud, Emanuele Valea, Jérôme Quévremont, Nicolas Valette, Paolo Maistri, Régis Leveugle, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre, Giorgio Di Natale:
A Comprehensive Approach to a Trusted Test Infrastructure. IVSW 2019: 43-48 - 2018
- [j17]Régis Leveugle, Asma Mkhinini, Paolo Maistri:
Hardware Support for Security in the Internet of Things: From Lightweight Countermeasures to Accelerated Homomorphic Encryption. Inf. 9(5): 114 (2018) - [c107]Jean-Max Dutertre, Vincent Beroulle, Philippe Candelier, Stephan De Castro, Louis-Barthelemy Faber, Marie-Lise Flottes, Philippe Gendrier, David Hély, Régis Leveugle, Paolo Maistri, Giorgio Di Natale, Athanasios Papadimitriou, Bruno Rouzeyre:
Laser Fault Injection at the CMOS 28 nm Technology Node: an Analysis of the Fault Model. FDTC 2018: 1-6 - [c106]Jean-Max Dutertre, Vincent Beroulle, Philippe Candelier, Louis-Barthelemy Faber, Marie-Lise Flottes, Philippe Gendrier, David Hély, Régis Leveugle, Paolo Maistri, Giorgio Di Natale, Athanasios Papadimitriou, Bruno Rouzeyre:
The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks. IOLTS 2018: 214-219 - 2017
- [c105]Asma Mkhinini, Paolo Maistri, Régis Leveugle, Rached Tourki:
HLS design of a hardware accelerator for Homomorphic Encryption. DDECS 2017: 178-183 - [c104]Giorgio Di Natale, Maha Kooli, Alberto Bosio, Michele Portolan, Régis Leveugle:
Reliability of computing systems: From flip flops to variables. IOLTS 2017: 196-198 - 2016
- [j16]Simon Pontie, Paolo Maistri, Régis Leveugle:
Dummy operations in scalar multiplication over elliptic curves: A tradeoff between security and performance. Microprocess. Microsystems 47: 23-36 (2016) - [j15]Athanasios Papadimitriou, David Hély, Vincent Beroulle, Paolo Maistri, Régis Leveugle:
Analysis of laser-induced errors: RTL fault models versus layout locality characteristics. Microprocess. Microsystems 47: 64-73 (2016) - [c103]Charalampos Ananiadis, Athanasios Papadimitriou, David Hély, Vincent Beroulle, Paolo Maistri, Régis Leveugle:
On the development of a new countermeasure based on a laser attack RTL fault model. DATE 2016: 445-450 - [c102]Simon Pontie, Alban Bourge, Adrien Prost-Boucle, Paolo Maistri, Olivier Muller, Régis Leveugle, Frédéric Rousseau:
HLS-Based Methodology for Fast Iterative Development Applied to Elliptic Curve Arithmetic. DSD 2016: 511-518 - [c101]Lydie Terras, Yannick Teglia, Michel Agoyan, Régis Leveugle:
Taking into account indirect jumps or calls in continuous control-flow checking. IDT 2016: 125-130 - [c100]Asma Mkhinini, Paolo Maistri, Régis Leveugle, Rached Tourki, Mohsen Machhout:
A flexible RNS-based large polynomial multiplier for Fully Homomorphic Encryption. IDT 2016: 131-136 - [c99]Régis Leveugle:
Tutorial 1: "New approaches towards early dependability evaluation of digital integrated systems". IDT 2016: xv - [c98]K. Chibani, Michele Portolan, Régis Leveugle:
Evaluating application-aware soft error effects in digital circuits without fault injections or probabilistic computations. IOLTS 2016: 54-59 - [c97]Régis Leveugle, A. Chahed, Paolo Maistri, Athanasios Papadimitriou, David Hély, Vincent Beroulle:
On fault injections for early security evaluation vs. laser-based attacks. IVSW 2016: 1-6 - 2015
- [c96]Athanasios Papadimitriou, Marios Tampas, David Hély, Vincent Beroulle, Paolo Maistri, Régis Leveugle:
Validation of RTL laser fault injection model with respect to layout information. HOST 2015: 78-81 - [c95]C. Jayet-Griffon, Marie-Angela Cornelie, Paolo Maistri, Philippe Elbaz-Vincent, Régis Leveugle:
Polynomial multipliers for fully homomorphic encryption on FPGA. ReConFig 2015: 1-6 - 2014
- [c94]Athanasios Papadimitriou, David Hély, Vincent Beroulle, Paolo Maistri, Régis Leveugle:
A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks. DATE 2014: 1-4 - [c93]Simon Pontie, Paolo Maistri, Régis Leveugle:
An Elliptic Curve Crypto-Processor Secured by Randomized Windows. DSD 2014: 535-542 - [c92]Diego Alberto, Paolo Maistri, Régis Leveugle:
Electromagnetic attacks on embedded devices: A model of probe-circuit power coupling. DTIS 2014: 1-6 - [c91]Pierre Vanhauwaert, Paolo Maistri, Régis Leveugle, Athanasios Papadimitriou, David Hély, Vincent Beroulle:
On error models for RTL security evaluations. DTIS 2014: 1-6 - [c90]K. Chibani, Salma Bergaoui, Michele Portolan, Régis Leveugle:
Criticality evaluation of embedded software running on a pipelined microprocessor and impact of compilation options. ICECS 2014: 778-781 - [c89]Salma Bergaoui, Pierre Vanhauwaert, Régis Leveugle:
IDSM: An improved disjoint signature monitoring scheme for processor behavioral checking. LATW 2014: 1-6 - [c88]K. Chibani, Mohamed Ben Jrad, Michele Portolan, Régis Leveugle:
Fast accurate evaluation of register lifetime and criticality in a pipelined microprocessor. VLSI-SoC 2014: 1-6 - [c87]Régis Leveugle, Paolo Maistri, Pierre Vanhauwaert, Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Athanasios Papadimitriou, David Hély, Vincent Beroulle, Guillaume Hubert, Stephan De Castro, Jean-Max Dutertre, Alexandre Sarafianos, Noemie Boher, Mathieu Lisart, Joel Damiens, Philippe Candelier, Clément Tavernier:
Laser-induced fault effects in security-dedicated circuits. VLSI-SoC 2014: 1-6 - [c86]Paolo Maistri, Régis Leveugle, Lilian Bossuet, Alain Aubert, Viktor Fischer, Bruno Robisson, Nicolas Moro, Philippe Maurine, Jean-Max Dutertre, Mathieu Lisart:
Electromagnetic analysis and fault injection onto secure circuits. VLSI-SoC 2014: 1-6 - [c85]Vincent Beroulle, Philippe Candelier, Stephan De Castro, Giorgio Di Natale, Jean-Max Dutertre, Marie-Lise Flottes, David Hély, Guillaume Hubert, Régis Leveugle, Feng Lu, Paolo Maistri, Athanasios Papadimitriou, Bruno Rouzeyre, Clément Tavernier, Pierre Vanhauwaert:
Laser-Induced Fault Effects in Security-Dedicated Circuits. VLSI-SoC (Selected Papers) 2014: 220-240 - 2013
- [j14]Salma Bergaoui, A. Wecxsteen, Régis Leveugle:
Detailed Analysis of Compilation Options for Robust Software-based Embedded Systems. J. Electron. Test. 29(2): 211-222 (2013) - [j13]Diego Alberto, Paolo Maistri, Régis Leveugle:
Forecasting the Effects of Electromagnetic Fault Injections on Embedded Cryptosystems. Inf. Secur. J. A Glob. Perspect. 22(5-6): 237-243 (2013) - [c84]Paolo Maistri, Sébastien Tiran, Philippe Maurine, Israel Koren, Régis Leveugle:
An evaluation of an AES implementation protected against EM analysis. ACM Great Lakes Symposium on VLSI 2013: 317-318 - [c83]Mohamed Ben Jrad, Régis Leveugle:
Evaluating a low cost robustness improvement in SRAM-based FPGAs. IOLTS 2013: 173-174 - [c82]Mohamed Ben Jrad, Régis Leveugle:
Automated design flow for no-cost configuration error detection in sram-based FPGAs. ReConFig 2013: 1-6 - [c81]Paolo Maistri, Sébastien Tiran, Philippe Maurine, Israel Koren, Régis Leveugle:
Countermeasures against EM analysis for a secured FPGA-based AES implementation. ReConFig 2013: 1-6 - 2012
- [c80]Mohamed Ben Jrad, Régis Leveugle:
Pattern-based injections in processors implemented on SRAM-based FPGAs. LATW 2012: 1-4 - [c79]A. Wecxsteen, Salma Bergaoui, Régis Leveugle:
Detailed analysis of compilation options for robust software-based embedded systems. LATW 2012: 1-6 - 2011
- [j12]Gaetan Canivet, Paolo Maistri, Régis Leveugle, Jessy Clédière, Florent Valette, Marc Renaudin:
Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA. J. Cryptol. 24(2): 247-268 (2011) - [c78]Salma Bergaoui, Régis Leveugle:
Impact of Software Optimization on Variable Lifetimes in a Microprocessor-Based System. DELTA 2011: 56-61 - [c77]Paolo Maistri, Régis Leveugle:
10-Gigabit Throughput and Low Area for a Hardware Implementation of the Advanced Encryption Standard. DSD 2011: 266-269 - [c76]Renaud Clavel, Laurence Pierre, Régis Leveugle:
Towards Robustness Analysis Using PVS. ITP 2011: 71-86 - 2010
- [c75]Gaetan Canivet, Paolo Maistri, Régis Leveugle, Frédéric Valette, Jessy Clédière, Marc Renaudin:
Dependability analysis of a countermeasure against fault attacks by means of laser shots onto a SRAM-based FPGA. ASAP 2010: 115-122 - [c74]Gaetan Canivet, P. Maistn, Régis Leveugle, Frédéric Valette, Jessy Clédière, Marc Renaudin:
Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA. ETS 2010: 251 - [c73]Régis Leveugle:
Early Robustness Evaluation of Digital Integrated Systems. FDL 2010: 69-70 - [c72]Régis Leveugle, Mohamed Ben Jrad:
A new methodology for accurate predictive robustness analysis of designs implemented in SRAM-based FPGAs. ICECS 2010: 1172-1175
2000 – 2009
- 2009
- [c71]Régis Leveugle, A. Calvez, Paolo Maistri, Pierre Vanhauwaert:
Statistical fault injection: Quantified error and confidence. DATE 2009: 502-506 - [c70]Souheib Baarir, Cécile Braunstein, Renaud Clavel, Emmanuelle Encrenaz, Jean-Michel Ilié, Régis Leveugle, Isabelle Mounier, Laurence Pierre, Denis Poitrenaud:
Complementary Formal Approaches for Dependability Analysis. DFT 2009: 331-339 - [c69]Paolo Maistri, Régis Leveugle:
Towards automated fault pruning with Petri Nets. IOLTS 2009: 41-46 - [c68]Gaetan Canivet, Régis Leveugle, Jessy Clédière, Frédéric Valette, Marc Renaudin:
Characterization of Effective Laser Spots during Attacks in the Configuration of a Virtex-II FPGA. VTS 2009: 327-332 - 2008
- [j11]Paolo Maistri, Régis Leveugle:
Double-Data-Rate Computation as a Countermeasure against Fault Analysis. IEEE Trans. Computers 57(11): 1528-1539 (2008) - [c67]Régis Leveugle:
Chip level security: Why ? How ? ICECS 2008: 25-26 - [c66]Pierre Vanhauwaert, Michele Portolan, Régis Leveugle, Philippe Roche:
Usefulness and effectiveness of HW and SW protection mechanisms in a processor-based system. ICECS 2008: 113-116 - [c65]Paolo Maistri, Cyril Excoffon, Régis Leveugle:
Software BIST capabilities of a symmetric cipher. ICECS 2008: 414-417 - [c64]Paolo Maistri, Cyril Excoffon, Régis Leveugle:
Software Self-Testing of a Symmetric Cipher with Error Detection Capability. IOLTS 2008: 79-84 - [c63]Gaetan Canivet, Jessy Clédière, Jean Baptiste Ferron, Frédéric Valette, Marc Renaudin, Régis Leveugle:
Detailed Analyses of Single Laser Shot Effects in the Configuration of a Virtex-II FPGA. IOLTS 2008: 289-294 - 2007
- [j10]V. Maingot, Jean Baptiste Ferron, Régis Leveugle, Vincent Pouget, Alexandre Douin:
Configuration errors analysis in SRAM-based FPGAs: Software tool and practical results. Microelectron. Reliab. 47(9-11): 1836-1840 (2007) - [j9]Régis Leveugle:
Early Analysis of Fault-based Attack Effects in Secure Circuits. IEEE Trans. Computers 56(10): 1431-1434 (2007) - [j8]Ian O'Connor, Junchen Liu, Frédéric Gaffiot, Fabien Prégaldiny, Christophe Lallement, Cristell Maneux, Johnny Goguet, Sébastien Fregonese, Thomas Zimmer, Lorena Anghel, Trong-Trinh Dang, Régis Leveugle:
CNTFET Modeling and Reconfigurable Logic-Circuit Design. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(11): 2365-2379 (2007) - [c62]Régis Leveugle, Abdelaziz Ammari, V. Maingot, E. Teyssou, Pascal Moitrel, Christophe Mourtel, Nathalie Feyt, Jean-Baptiste Rigaud, Assia Tria:
Experimental evaluation of protections against laser-induced faults and consequences on fault modeling. DATE 2007: 1587-1592 - [c61]Michele Portolan, Régis Leveugle:
Effective Checkpoint and Rollback Using Hardware/OS Collaboration. DFT 2007: 370-378 - [c60]Paolo Maistri, Pierre Vanhauwaert, Régis Leveugle:
Evaluation of Register-Level Protection Techniques for the Advanced Encryption Standard by Multi-Level Fault Injections. DFT 2007: 499-507 - [c59]Paolo Maistri, Pierre Vanhauwaert, Régis Leveugle:
A Novel Double-Data-Rate AES Architecture Resistant against Fault Injection. FDTC 2007: 54-61 - [c58]Régis Leveugle:
Dependability issues in SRAM-based FPGA design. ICECS 2007: 1 - [c57]Christophe Smekens, Régis Leveugle:
On Deratings to Refine System-Level Failure Rate Estimations. ICECS 2007: 326-329 - [c56]Yannick Monnet, Marc Renaudin, Régis Leveugle:
Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs. IOLTS 2007: 113-120 - 2006
- [j7]Yannick Monnet, Marc Renaudin, Régis Leveugle:
Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic. IEEE Trans. Computers 55(9): 1104-1115 (2006) - [c55]Régis Leveugle, V. Maingot:
On the Use of Information Redundancy When Designing Secure Chips. DDECS 2006: 141-142 - [c54]Pierre Vanhauwaert, Régis Leveugle, Philippe Roche:
A Flexible SoPC-based Fault Injection Environment. DDECS 2006: 192-197 - [c53]Abdelaziz Ammari, Régis Leveugle, Bogdan Nicolescu, Yvon Savaria:
Evaluation of a Software-Based Error Detection Technique by RT-Level Fault Injection. DELTA 2006: 488-493 - [c52]Yannick Monnet, Marc Renaudin, Régis Leveugle, Christophe Clavier, Pascal Moitrel:
Case Study of a Fault Attack on Asynchronous DES Crypto-Processors. FDTC 2006: 88-97 - [c51]Vincent Maingot, Régis Leveugle:
Error Detection Code Efficiency for Secure Chips. ICECS 2006: 561-564 - [c50]Yannick Monnet, Marc Renaudin, Régis Leveugle, Nathalie Feyt, Pascal Moitrel, F. M'Buwa Nzenguet:
Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor. IOLTS 2006: 125-130 - [c49]Pierre Vanhauwaert, Régis Leveugle, Philippe Roche:
Reduced Instrumentation and Optimized Fault Injection Control for Dependability Analysis. VLSI-SoC 2006: 391-396 - 2005
- [j6]Abdelaziz Ammari, K. Hadjiat, Régis Leveugle:
Combined Fault Classification and Error Propagation Analysis to Refine RT-Level Dependability Evaluation. J. Electron. Test. 21(4): 365-376 (2005) - [c48]Yannick Monnet, Marc Renaudin, Régis Leveugle:
Asynchronous circuits transient faults sensitivity evaluation. DAC 2005: 863-868 - [c47]Michele Portolan, Régis Leveugle:
Towards a Secure and Reliable System. EUC 2005: 1085-1098 - [c46]Régis Leveugle:
Introduction to the Special Session on Secure Implementations. IOLTS 2005: 115 - [c45]Yannick Monnet, Marc Renaudin, Régis Leveugle:
Hardening Techniques against Transient Faults for Asynchronous Circuits. IOLTS 2005: 129-134 - [c44]Régis Leveugle, Yervant Zorian, Luca Breveglieri, André K. Nieuwland, Klaus Rothbart, Jean-Pierre Seifert:
On-Line Testing for Secure Implementations: Design and Validation. IOLTS 2005: 211 - [c43]Michele Portolan, Régis Leveugle:
On the Need for Common Evaluation Methods for Fault Tolerance Costs in Microprocessors. IOLTS 2005: 247-252 - [c42]Régis Leveugle:
A New Approach for Early Dependability Evaluation Based on Formal Property Checking and Controlled Mutations. IOLTS 2005: 260-265 - [c41]Lorena Anghel, Régis Leveugle, Pierre Vanhauwaert:
Evaluation of SET and SEU Effects at Multiple Abstraction Levels. IOLTS 2005: 309-312 - 2004
- [c40]Régis Leveugle, Abdelaziz Ammari:
Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global Flow. DATE 2004: 590-595 - [c39]Régis Leveugle, D. Cimonnet, Abdelaziz Ammari:
System-Level Dependability Analysis with RT-Level Fault Injection Accuracy. DFT 2004: 451-458 - [c38]Yannick Monnet, Marc Renaudin, Régis Leveugle:
Asynchronous Circuits Sensitivity to Fault Injection. IOLTS 2004: 121-128 - [c37]Michele Portolan, Régis Leveugle:
Operating System Function Reuse to Achieve Low-Cost Fault Tolerance. IOLTS 2004: 167-174 - [c36]Abdelaziz Ammari, K. Hadjiat, Régis Leveugle:
On Combining Fault Classification and Error Propagation Analysis in RT-Level Dependability Evaluation. IOLTS 2004: 227-232 - 2003
- [j5]Régis Leveugle, K. Hadjiat:
Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments. J. Electron. Test. 19(5): 559-575 (2003) - [j4]Régis Leveugle, Glenn H. Chapman:
Special section on defect and fault tolerance in VLSI systems. Microelectron. J. 34(1): 1 (2003) - [j3]Lörinc Antoni, Régis Leveugle, Béla Fehér:
Using run-time reconfiguration for fault injection applications. IEEE Trans. Instrum. Meas. 52(5): 1468-1473 (2003) - [c35]Abdelaziz Ammari, Régis Leveugle, Matteo Sonza Reorda, Massimo Violante:
Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels. DFT 2003: 336-343 - [c34]Régis Leveugle, Lörinc Antoni, Béla Fehér:
Dependability Analysis: A New Application for Run-Time Reconfiguration. IPDPS 2003: 173 - 2002
- [c33]Régis Leveugle:
Automatic Modifications of High Level VHDL Descriptions for Fault Detection or Tolerance. DATE 2002: 837-841 - [c32]Lörinc Antoni, Régis Leveugle, Béla Fehér:
Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes. DFT 2002: 245-253 - [c31]Régis Leveugle, K. Hadjiat:
Multi-Level Fault Injection Experiments Based on VHDL Descriptions: A Case Study. IOLTW 2002: 107-111 - 2001
- [c30]Régis Leveugle, R. Cercueil:
High Level Modifications of VHDL Descriptions for On-Line Test or Fault Tolerance. DFT 2001: 84- - [c29]Régis Leveugle:
A Low-Cost Hardware Approach to Dependability Validation of Ips. DFT 2001: 242-249 - [c28]Raoul Velazco, Régis Leveugle, Oscar Calvo:
Upset-Like Fault Injection in VHDL Descriptions: A Method and Preliminary Results. DFT 2001: 259- - 2000
- [c27]Lörinc Antoni, Régis Leveugle, Béla Fehér:
Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes. DFT 2000: 405-413 - [c26]Régis Leveugle:
Fault Injection in VHDL Descriptions and Emulation. DFT 2000: 414- - [c25]Régis Leveugle, K. Hadjiat:
Optimized Generation of VHDL Mutants for Injection of Transition Errors. SBCCI 2000: 243-248
1990 – 1999
- 1999
- [c24]Alejandro Chagoya, Régis Leveugle:
Experiments on Multimedia Support of VLSI Design teaching in the MODEM Project. MSE 1999: 82-83 - 1997
- [c23]X. Wendling, H. Chauvet, Lionel Revéret, Raphaël Rochet, Régis Leveugle:
Automatic and Optimized Synthesis of Dataparts with Fault Detection or Tolerance Capabilities. DFT 1997: 195-203 - 1996
- [c22]X. Wendling, Raphaël Rochet, Régis Leveugle:
ROM-Based Synthesis of Fault-Tolerant Controllers. DFT 1996: 304-309 - [c21]X. Wendling, Raphaël Rochet, Régis Leveugle:
Standard and ROM-based synthesis of FSMs with control flow checking capabilities. VTS 1996: 81-86 - 1995
- [c20]Raphaël Rochet, Régis Leveugle, Gabriele Saucier:
Efficient synthesis of fault-tolerant controllers. ED&TC 1995: 593 - [c19]P. Brahic, Régis Leveugle, Gabriele Saucier:
Design of defect-tolerant scan chains for MCMs with an active substrate. DFT 1995: 252-260 - 1994
- [j2]Régis Leveugle, Zahava Koren, Israel Koren, Gabriele Saucier, Norbert Wehn:
The Hyeti Defect Tolerant Microprocessor: A Practical Experiment and its Cost-Effectiveness Analysis. IEEE Trans. Computers 43(12): 1398-1406 (1994) - [c18]Régis Leveugle, Raphaël Rochet, Gabriele Saucier:
Alternative Approaches to Fault Detection in FSMs. DFT 1994: 271-279 - [c17]T. Michel, Régis Leveugle, Gabriele Saucier, R. Doucet, P. Chapier:
Taking Advantage of ASICs to Improve Dependability with Very Low Overheads. EDAC-ETC-EUROASIC 1994: 14-18 - [c16]C. Safinia, Régis Leveugle, Gabriele Saucier:
Taking Advantage of High Level Functional Information to Refine Timing Analysis and Timing Modeling. EDAC-ETC-EUROASIC 1994: 349-353 - 1993
- [c15]Régis Leveugle:
Optimized State Assignment of single fault Tolerant FSMs Based on SEC Codes. DAC 1993: 14-18 - [c14]Raphaël Rochet, Régis Leveugle, Gabriele Saucier:
Analysis and Comparison of Fault Tolerant FSM Architectures Based on SEC Codes. DFT 1993: 9-16 - [c13]Régis Leveugle, Raphaël Rochet, Gabriele Saucier, L. Martinez, C. Pitot:
A Synthesis Tool for Fault-Tolerant Finite State Machines. FTCS 1993: 502-511 - [c12]Régis Leveugle, X. Delord, Gabriele Saucier:
Influence of Error Correlations on the Signature Analysis Aliasing. ICCD 1993: 584-587 - [c11]Régis Leveugle:
Test of single fault tolerant controllers in VLSI circuits. VLSI 1993: 123-132 - 1992
- [c10]Laurent Gerbaux, Régis Leveugle, Gabriele Saucier:
Synthesis of large controllers using ROM or PLA generators. Synthesis for Control Dominated Circuits 1992: 47-59 - [c9]Régis Leveugle, C. Safina:
Generation of optimized datapaths: bit-slice versus standard cells. Synthesis for Control Dominated Circuits 1992: 153-166 - [c8]C. Safina, Régis Leveugle:
Clocking scheme selection for circuits made up of a controller and a datapath. Synthesis for Control Dominated Circuits 1992: 293-308 - [c7]Pierre Abouzeid, Régis Leveugle, Gabriele Saucier:
Logic Synthesis for Automatic Layout. Synthesis for Control Dominated Circuits 1992: 335-343 - 1991
- [c6]T. Michel, Régis Leveugle, Gabriele Saucier:
A New Approach to Control Flow Checking Without Program Modification. FTCS 1991: 334-343 - [c5]Margot Karam, Régis Leveugle, Gabriele Saucier:
Hierarchical Test Generation Based on Delayed Propagation. ITC 1991: 739-747 - 1990
- [j1]Régis Leveugle, Gabriele Saucier:
Optimized Synthesis of Concurrently Checked Controllers. IEEE Trans. Computers 39(4): 419-425 (1990) - [c4]Régis Leveugle, T. Michel, Gabriele Saucier:
Design of microprocessors with built-in on-line test. FTCS 1990: 450-456
1980 – 1989
- 1989
- [c3]Gabriele Saucier, Régis Leveugle, Pierre Abouzeid:
A channelless layout for multilevel synthesis with compiled cells. ICCD 1989: 35-38 - [c2]Régis Leveugle, Gabriele Saucier:
Concurrent checking in dedicated controllers. ICCD 1989: 124-127 - [c1]Régis Leveugle, Gabriele Saucier:
Optimized Synthesis of Dedicated Controllers with Concurrent Checking Capabilities. ITC 1989: 355-363
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-07 21:24 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
