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ORCIDHidemasa Kubota
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2000 – 2009
- 2007
[j3]Takayuki Watanabe, Yuichi Tanji, Hidemasa Kubota, Hideki Asai
:
Fast Transient Simulation of Power Distribution Networks Containing Dispersion Based on Parallel-Distributed Leapfrog Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(2): 388-397 (2007)- 2006
- [j2]Hidemasa Kubota, Yuichi Tanji, Takayuki Watanabe, Hideki Asai:
An Enhanced Time-Domain Circuit Simulation Technique Based on LIM. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(5): 1505-1506 (2006) - [c9]Takayuki Watanabe, Yuichi Tanji, Hidemasa Kubota, Hideki Asai:
Parallel-distributed time-domain circuit simulation of power distribution networks with frequency-dependent parameters. ASP-DAC 2006: 832-837 - [c8]Yuichi Tanji, Takayuki Watanabe, Hidemasa Kubota, Hideki Asai:
Large scale RLC circuit analysis using RLCG-MNA formulation. DATE 2006: 45-46 - [c7]Yuichi Tanji, Takayuki Watanabe, Hidemasa Kubota, Hideki Asai:
Quasi-One-Step Gauss-Jacobi Method for Large-Scale Interconnect Analysis via RLCG-MNA Formulation. ISQED 2006: 393-400 - 2005
- [c6]Hidemasa Kubota, Yuichi Tanji, Takayuki Watanabe, Hideki Asai:
Generalized method of the time-domain circuit simulation based on LIM with MNA formulation. CICC 2005: 289-292 - [c5]Hirofumi Suzuki, Hidemasa Kubota, Takayuki Watanabe, Hideki Asai:
Interconnect simulation using FDTD method with variable mesh size technique. ECCTD 2005: 225-228 - [c4]Takashi Mine, Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai:
Modified hybrid reduction technique for the simulation of linear/nonlinear mixed circuits. ISCAS (5) 2005: 4903-4906 - [c3]Yuichi Tanji, Hidemasa Kubota:
Passive approximation of tabulated frequency-data by Fourier expansion method. ISCAS (6) 2005: 5762-5765 - 2004
- [c2]Takashi Mine, Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai:
Hybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed Circuits. DATE 2004: 1327-1333 - 2002
- [j1]Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai:
An Efficient Simulator for Multiport Interconnects with Model Order Reduction Technique. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(6): 1214-1219 (2002) - [c1]Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai:
Noise analysis of power/ground planes on PCB by SPICE-like simulator with model order reduction technique. ISCAS (5) 2002: 649-552
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