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ORCIDMitsuyasu Ohta
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2000 – 2009
- 2002
[c7]Masayoshi Yoshimura, Toshinori Hosokawa, Mitsuyasu Ohta:
A Test Point Insertion Method to Reduce the Number of Test Patterns. Asian Test Symposium 2002: 298-304- 2001
- [c6]Toshinori Hosokawa, Masayoshi Yoshimura, Mitsuyasu Ohta:
Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times. ASP-DAC 2001: 485-491 - [c5]Tetsuji Kishi, Mitsuyasu Ohta, Takashi Taniguchi, Hiroshi Kadota:
A New Inter-Core Built-In-Self-Test Circuits for Tri-State Buffers in the System on a Chip. Asian Test Symposium 2001: 462 - 2000
- [c4]Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara, Atsushi Murakami, Sadami Takeoka, Mitsuyasu Ohta:
On validating data hold times for flip-flops in sequential circuits. ITC 2000: 317-325
1990 – 1999
- 1997
- [c3]Toshinori Hosokawa, Toshihiro Hiraoka, Mitsuyasu Ohta, Michiaki Muraoka, Shigeo Kuninobu:
A Partial Scan Design Method Based on n-Fold Line-up Structures. Asian Test Symposium 1997: 306- - 1996
- [c2]Toshinori Hosokawa, Kenichi Kawaguchi, Mitsuyasu Ohta, Michiaki Muraoka:
A Design for testability Method Using RTL Partitioning. Asian Test Symposium 1996: 88-93 - 1995
- [c1]Akira Motohara, Sadami Takeoka, Toshinori Hosokawa, Mitsuyasu Ohta, Yuji Takai, Michihiro Matsumoto, Michiaki Muraoka:
Design for testability using register-transfer level partial scan selection. ASP-DAC 1995
Coauthor Index
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