default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDSeiji Kajihara
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
[j52]Joshua Adiel Wijaya
, Poki Chen, Lucky Kumar Pradhan, Ahmad Shahid Bhatti, Seiji Kajihara:
Area Efficient 0.009-mm2 28.1-ppm/°C 11.3-MHz ALL-MOS Relaxation Oscillator. IEEE Trans. Very Large Scale Integr. Syst. 32(10): 1900-1907 (2024)- 2022
- [j51]Poki Chen, Joshua Adiel Wijaya, Seiji Kajihara, Trio Adiono, Hsiang-Yu Chen, Ruei-Ting Wang, Yousuke Miyake:
A 1-ps Bin Size 4.87-ps Resolution FPGA Time-to-Digital Converter Based on Phase Wrapping Sorting and Selection. IEEE Access 10: 126429-126439 (2022) - [c109]Takaaki Kato, Yousuke Miyake, Seiji Kajihara:
On Correction of A Delay Value Using Ring-Oscillators for Aging Detection and Prediction. ATS 2022: 60-65 - [c108]Kazuya Loki, Yasuyuki Kai, Kohei Miyase, Seiji Kajihara:
A Practical Online Error Detection Method for Functional Safety Using Three-Site Implications. ITC 2022: 63-72 - [c107]Taiki Utsunomiya, Ryu Hoshino, Kohei Miyase, Shyue-Kung Lu, Xiaoqing Wen, Seiji Kajihara:
Effective Switching Probability Calculation to Locate Hotspots in Logic Circuits. ITC-Asia 2022: 43-48 - 2021
- [j50]Yucong Zhang, Stefan Holst, Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Jun Qian:
On the Efficacy of Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption. IEICE Trans. Inf. Syst. 104-D(6): 816-827 (2021) - 2020
- [j49]Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara, Xiaoqing Wen:
A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips. IEEE Trans. Emerg. Top. Comput. 8(3): 591-601 (2020) - [j48]Poki Chen, Jian-Ting Lan, Ruei-Ting Wang, Nguyen My Qui, John Carl Joel Salao Marquez, Seiji Kajihara, Yousuke Miyake:
High-Precision PLL Delay Matrix With Overclocking and Double Data Rate for Accurate FPGA Time-to-Digital Converters. IEEE Trans. Very Large Scale Integr. Syst. 28(4): 904-913 (2020) - [c106]Masayuki Gondo, Yousuke Miyake, Takaaki Kato, Seiji Kajihara:
On Evaluation for Aging-Tolerant Ring Oscillators with Accelerated Life Test And Its Application to A Digital Sensor. ATS 2020: 1-6 - [c105]Yousuke Miyake, Takaaki Kato, Seiji Kajihara, Masao Aso, Haruji Futami, Satoshi Matsunaga, Yukiya Miura:
On-Chip Delay Measurement for Degradation Detection And Its Evaluation under Accelerated Life Test. IOLTS 2020: 1-6 - [c104]Yousuke Miyake, Takaaki Kato, Seiji Kajihara:
Path Delay Measurement with Correction for Temperature And Voltage Variations. ITC-Asia 2020: 112-117 - [c103]Takeshi Iwasaki, Masao Aso, Haruji Futami, Satoshi Matsunaga, Yousuke Miyake, Takaaki Kato, Seiji Kajihara, Yukiya Miura, Smith Lai, Gavin Hung, Harry H. Chen, Haruo Kobayashi, Kazumi Hatayama:
Innovative Test Practices in Asia. VTS 2020: 1
2010 – 2019
- 2019
- [c102]Shoi Tachibana, Shunsuke Araki, Seiji Kajihara, Shigeyuki Azuchi, Yukishige Nakajo, Hideki Shoda:
FPGA implementation of ECDSA for Blockchain. ICCE-TW 2019: 1-2 - [c101]Yousuke Miyake, Yasuo Sato, Seiji Kajihara:
A Selection Method of Ring Oscillators for An On-Chip Digital Temperature And Voltage Sensor. ITC-Asia 2019: 13-18 - [c100]Kohei Miyase, Yudai Kawano, Shyue-Kung Lu, Xiaoqing Wen, Seiji Kajihara:
A Static Method for Analyzing Hotspot Distribution on the LSI. ITC-Asia 2019: 73-78 - [c99]Yousuke Miyake, Seiji Kajihara, Poki Chen:
On-Chip Test Clock Validation Using A Time-to-Digital Converter in FPGAs. ITC-Asia 2019: 157-162 - [c98]Yousuke Miyake, Yasuo Sato, Seiji Kajihara:
On-Chip Delay Measurement for In-Field Test of FPGAs. PRDC 2019: 130-137 - 2018
- [c97]Shigeyuki Oshima, Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara:
On Flip-Flop Selection for Multi-cycle Scan Test with Partial Observation in Logic BIST. ATS 2018: 30-35 - [c96]Yucong Zhang, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Hans-Joachim Wunderlich, Jun Qian:
Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing. ATS 2018: 149-154 - [c95]Takeru Nishimi, Yasuo Sato, Seiji Kajihara, Yoshiyuki Nakamura:
Good Die Prediction Modelling from Limited Test Items. ITC-Asia 2018: 115-120 - 2017
- [c94]Yucong Zhang, Stefan Holst, Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Jun Qian:
Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption. ATS 2017: 145-150 - [c93]Stefan Holst, Eric Schneider, Koshi Kawagoe, Michael A. Kochte, Kohei Miyase, Hans-Joachim Wunderlich, Seiji Kajihara, Xiaoqing Wen:
Analysis and mitigation or IR-Drop induced scan shift-errors. ITC 2017: 1-8 - [c92]Yousuke Miyake, Yasuo Sato, Seiji Kajihara:
On the effects of real time and contiguous measurement with a digital temperature and voltage sensor. ITC-Asia 2017: 125-130 - 2016
- [j47]Fuqiang Li, Xiaoqing Wen, Kohei Miyase, Stefan Holst, Seiji Kajihara:
Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2310-2319 (2016) - [j46]Yousuke Miyake, Yasuo Sato, Seiji Kajihara, Yukiya Miura:
Temperature and Voltage Measurement for Field Test Using an Aging-Tolerant Monitor. IEEE Trans. Very Large Scale Integr. Syst. 24(11): 3282-3295 (2016) - [c91]Stefan Holst, Eric Schneider, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Hans-Joachim Wunderlich, Michael A. Kochte:
Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test. ATS 2016: 19-24 - [c90]Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara, Xiaoqing Wen:
A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST. ATS 2016: 203-208 - 2015
- [j45]Senling Wang, Yasuo Sato, Seiji Kajihara, Hiroshi Takahashi:
Physical Power Evaluation of Low Power Logic-BIST Scheme Using Test Element Group Chip. J. Low Power Electron. 11(4): 528-540 (2015) - [c89]Koji Asada, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Michael A. Kochte, Eric Schneider, Hans-Joachim Wunderlich, Jun Qian:
Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch. ATS 2015: 103-108 - [c88]Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara:
Identification of high power consuming areas with gate type and logic level information. ETS 2015: 1-6 - 2014
- [j44]Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Kohei Miyase, Stefan Holst, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang:
On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST. IEICE Trans. Inf. Syst. 97-D(10): 2706-2718 (2014) - [c87]Shyue-Kung Lu, Hao-Cheng Jheng, Hao-Wei Lin, Masaki Hashizume, Seiji Kajihara:
Built-In Scrambling Analysis for Yield Enhancement of Embedded Memories. ATS 2014: 137-142 - [c86]Yousuke Miyake, Yasuo Sato, Seiji Kajihara, Yukiya Miura:
Temperature and Voltage Estimation Using Ring-Oscillator-Based Monitor for Field Test. ATS 2014: 156-161 - [c85]Seiji Kajihara, Yousuke Miyake, Yasuo Sato, Yukiya Miura:
An On-Chip Digital Environment Monitor for Field Test. ATS 2014: 254-257 - [c84]Yasuo Sato, Masafumi Monden, Yousuke Miyake, Seiji Kajihara:
Reduction of NBTI-Induced Degradation on Ring Oscillators in FPGA. PRDC 2014: 59-67 - 2013
- [j43]Yuta Yamato, Kohei Miyase, Seiji Kajihara, Xiaoqing Wen, Laung-Terng Wang, Michael A. Kochte:
LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing. IEEE Des. Test 30(4): 60-70 (2013) - [j42]Kohei Miyase, Ryota Sakai, Xiaoqing Wen, Masao Aso, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara:
A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing. IEICE Trans. Inf. Syst. 96-D(9): 2003-2011 (2013) - [j41]Senling Wang, Yasuo Sato, Seiji Kajihara, Kohei Miyase:
Scan-Out Power Reduction for Logic BIST. IEICE Trans. Inf. Syst. 96-D(9): 2012-2020 (2013) - [c83]Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang:
On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST. Asian Test Symposium 2013: 19-24 - [c82]Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara:
Search Space Reduction for Low-Power Test Generation. Asian Test Symposium 2013: 171-176 - [c81]Yasuo Sato, Seiji Kajihara:
A Stochastic Model for NBTI-Induced LSI Degradation in Field. Asian Test Symposium 2013: 183-188 - [c80]Kazunari Enokimoto, Xiaoqing Wen, Kohei Miyase, Jiun-Lang Huang, Seiji Kajihara, Laung-Terng Wang:
On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression. VLSI Design 2013: 279-284 - 2012
- [j40]Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara:
A Failure Prediction Strategy for Transistor Aging. IEEE Trans. Very Large Scale Integr. Syst. 20(11): 1951-1959 (2012) - [c79]Yasuo Sato, Senling Wang, Takaaki Kato, Kohei Miyase, Seiji Kajihara:
Low Power BIST for Scan-Shift and Capture Power. Asian Test Symposium 2012: 173-178 - [c78]Senling Wang, Yasuo Sato, Kohei Miyase, Seiji Kajihara:
A Scan-Out Power Reduction Method for Multi-cycle BIST. Asian Test Symposium 2012: 272-277 - [c77]Yukiya Miura, Yasuo Sato, Yousuke Miyake, Seiji Kajihara:
On-chip temperature and voltage measurement for field testing. ETS 2012: 1 - [c76]Yasuo Sato, Seiji Kajihara, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue, Yukiya Miura, Satosni Untake, Takumi Hasegawa, Motoyuki Sato, Kotaro Shimamura:
DART: Dependable VLSI test architecture and its implementation. ITC 2012: 1-10 - [c75]Xiaoqing Wen, Y. Nishida, Kohei Miyase, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang:
On pinpoint capture power management in at-speed scan test generation. ITC 2012: 1-10 - [c74]Kohei Miyase, Masao Aso, Ryou Ootsuka, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Kazunari Enokimoto, Seiji Kajihara:
A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits. VTS 2012: 197-202 - 2011
- [j39]Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Hiroshi Furukawa, Seiji Kajihara:
A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing. IEICE Trans. Inf. Syst. 94-D(4): 833-840 (2011) - [j38]Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara:
Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing. IEICE Trans. Inf. Syst. 94-D(6): 1216-1226 (2011) - [j37]Seiji Kajihara, Satoshi Ohtake, Tomokazu Yoneda:
Delay Testing: Improving Test Quality and Avoiding Over-testing. Inf. Media Technol. 6(4): 1053-1066 (2011) - [j36]Seiji Kajihara, Satoshi Ohtake, Tomokazu Yoneda:
Delay Testing: Improving Test Quality and Avoiding Over-testing. IPSJ Trans. Syst. LSI Des. Methodol. 4: 117-130 (2011) - [c73]Yasuo Sato, Hisato Yamaguchi, Makoto Matsuzono, Seiji Kajihara:
Multi-cycle Test with Partial Observation on Scan-Based BIST Structure. Asian Test Symposium 2011: 54-59 - [c72]Kohei Miyase, Y. Uchinodan, Kazunari Enokimoto, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara, Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Virazel:
Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling. Asian Test Symposium 2011: 90-95 - [c71]Kohei Miyase, Xiaoqing Wen, Masao Aso, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara:
Transition-Time-Relation based capture-safety checking for at-speed scan test generation. DATE 2011: 895-898 - [c70]Xiaoxin Fan, Sudhakar M. Reddy, Senling Wang, Seiji Kajihara, Yasuo Sato:
Genetic algorithm based approach for segmented testing. DSN Workshops 2011: 85-90 - [c69]Michael A. Kochte, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Kazunari Enokimoto, Hans-Joachim Wunderlich:
SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures. ISLPED 2011: 33-38 - [c68]Yuta Yamato, Xiaoqing Wen, Michael A. Kochte, Kohei Miyase, Seiji Kajihara, Laung-Terng Wang:
A novel scan segmentation design method for avoiding shift timing failure in scan testing. ITC 2011: 1-8 - [c67]Xiaoqing Wen, Kazunari Enokimoto, Kohei Miyase, Yuta Yamato, Michael A. Kochte, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor:
Power-aware test generation with guaranteed launch safety for at-speed scan testing. VTS 2011: 166-171 - 2010
- [j35]Kohei Miyase, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor:
High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme. IEICE Trans. Inf. Syst. 93-D(1): 2-9 (2010) - [j34]Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Atsushi Takashima, Hiroshi Furukawa, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja:
A Study of Capture-Safe Test Generation Flow for At-Speed Testing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(7): 1309-1318 (2010) - [j33]Shinji Oku, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen:
On Delay Test Quality for Test Cubes. Inf. Media Technol. 5(4): 1147-1155 (2010) - [j32]Shinji Oku, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen:
On Delay Test Quality for Test Cubes. IPSJ Trans. Syst. LSI Des. Methodol. 3: 283-291 (2010) - [c66]Mitsumasa Noda, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen, Yukiya Miura:
On estimation of NBTI-Induced delay degradation. ETS 2010: 107-111 - [c65]Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara:
Aging test strategy and adaptive test scheduling for SoC failure prediction. IOLTS 2010: 21-26
2000 – 2009
- 2009
- [c64]Kazunari Enokimoto, Xiaoqing Wen, Yuta Yamato, Kohei Miyase, H. Sone, Seiji Kajihara, Masao Aso, Hiroshi Furukawa:
CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing. Asian Test Symposium 2009: 99-104 - [c63]Kohei Miyase, Yuta Yamato, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Xiaoqing Wen, Seiji Kajihara:
A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment. ICCAD 2009: 97-104 - [c62]Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Hiroshi Furukawa, Seiji Kajihara:
A GA-Based Method for High-Quality X-Filling to Reduce Launch Switching Activity in At-speed Scan Testing. PRDC 2009: 81-86 - 2008
- [j31]Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita:
Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing. J. Electron. Test. 24(4): 379-391 (2008) - [j30]Seiji Kajihara, Michiko Inoue:
Special Section on Test and Verification of VLSIs. IEICE Trans. Inf. Syst. 91-D(3): 640-641 (2008) - [j29]Yuta Yamato, Yusuke Nakamura, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara:
A Novel Per-Test Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits. IEICE Trans. Inf. Syst. 91-D(3): 667-674 (2008) - [j28]Kohei Miyase, Kenta Terashima, Xiaoqing Wen, Seiji Kajihara, Sudhakar M. Reddy:
On Detection of Bridge Defects with Stuck-at Tests. IEICE Trans. Inf. Syst. 91-D(3): 683-689 (2008) - [j27]Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo:
Estimation of Delay Test Quality and Its Application to Test Generation. Inf. Media Technol. 3(4): 717-728 (2008) - [j26]Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo:
Estimation of Delay Test Quality and Its Application to Test Generation. IPSJ Trans. Syst. LSI Des. Methodol. 1: 104-115 (2008) - [c61]Hiroshi Furukawa, Xiaoqing Wen, Kohei Miyase, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor:
CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing. ATS 2008: 397-402 - [c60]Ilia Polian, Kohei Miyase, Yusuke Nakamura, Seiji Kajihara, Piet Engelke, Bernd Becker, Stefan Spinner, Xiaoqing Wen:
Diagnosis of Realistic Defects Based on the X-Fault Model. DDECS 2008: 263-266 - [c59]Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Hiroshi Furukawa, Yuta Yamato, Atsushi Takashima, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja:
A Capture-Safe Test Generation Scheme for At-Speed Scan Testing. ETS 2008: 55-60 - [c58]Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara:
Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification. ICCAD 2008: 52-58 - 2007
- [j25]Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita:
A Novel ATPG Method for Capture Power Reduction during Scan Testing. IEICE Trans. Inf. Syst. 90-D(9): 1398-1405 (2007) - [c57]Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Yuji Ohsumi, Kewal K. Saluja:
Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing. DAC 2007: 527-532 - [c56]Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo:
Estimation of delay test quality and its application to test generation. ICCAD 2007: 413-417 - [c55]Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Tatsuya Suzuki, Yuta Yamato, Patrick Girard, Yuji Ohsumi, Laung-Terng Wang:
A novel scheme to reduce power supply noise for high-quality at-speed scan testing. ITC 2007: 1-10 - 2006
- [j24]Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Seiji Kajihara:
A Statistical Quality Model for Delay Testing. IEICE Trans. Electron. 89-C(3): 349-355 (2006) - [j23]Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita:
A New Method for Low-Capture-Power Test Generation for Scan Testing. IEICE Trans. Inf. Syst. 89-D(5): 1679-1686 (2006) - [j22]Yoshinobu Higami, Seiji Kajihara, Irith Pomeranz, Shin-ya Kobayashi, Yuzo Takamatsu:
On Finding Don't Cares in Test Sequences for Sequential Circuits. IEICE Trans. Inf. Syst. 89-D(11): 2748-2755 (2006) - [j21]Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Yuta Yamato, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita:
A Per-Test Fault Diagnosis Method Based on the X-Fault Model. IEICE Trans. Inf. Syst. 89-D(11): 2756-2765 (2006) - [c54]Masayasu Fukunaga, Seiji Kajihara, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato:
A dynamic test compaction procedure for high-quality path delay testing. ASP-DAC 2006: 348-353 - [c53]Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Yamato, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja:
Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation. ICCD 2006: 251-258 - [c52]Seiji Kajihara, Shohei Morishima, Akane Takuma, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato:
A Framework of High-quality Transition Fault ATPG for Scan Circuits. ITC 2006: 1-6 - [c51]Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita:
A New ATPG Method for Efficient Capture Power Reduction During Scan Testing. VTS 2006: 58-65 - 2005
- [j20]Xiaoqing Wen, Seiji Kajihara, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita:
On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies. IEICE Trans. Inf. Syst. 88-D(4): 703-710 (2005) - [j19]Masayasu Fukunaga, Seiji Kajihara, Sadami Takeoka:
On Statistical Estimation of Fault Efficiency for Path Delay Faults Based on Untestable Path Analysis. IEICE Trans. Inf. Syst. 88-D(7): 1671-1677 (2005) - [j18]Xiaoqing Wen, Tatsuya Suzuki, Seiji Kajihara, Kohei Miyase, Yoshihiro Minamoto, Laung-Terng Wang, Kewal K. Saluja:
Efficient Test Set Modification for Capture Power Reduction. J. Low Power Electron. 1(3): 319-330 (2005) - [j17]Yoshinobu Higami, Seiji Kajihara, Hideyuki Ichihara, Yuzo Takamatsu:
Test cost reduction for logic circuits: Reduction of test data volume and test application time. Syst. Comput. Jpn. 36(6): 69-83 (2005) - [c50]Yasumi Doi, Seiji Kajihara, Xiaoqing Wen, Lei Li, Krishnendu Chakrabarty:
Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation. ASP-DAC 2005: 59-64 - [c49]Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Seiji Kajihara:
Evaluation of the statistical delay quality model. ASP-DAC 2005: 305-310 - [c48]Kohei Miyase, Kenta Terashima, Seiji Kajihara, Xiaoqing Wen, Sudhakar M. Reddy:
On Improving Defect Coverage of Stuck-at Fault Tests. Asian Test Symposium 2005: 216-223 - [c47]Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato:
Path delay test compaction with process variation tolerance. DAC 2005: 845-850 - [c46]Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Yasuyuki Nozuyama, Seiji Kajihara:
Invisible delay quality - SDQM model lights up what could not be seen. ITC 2005: 9 - [c45]Xiaoqing Wen, Yoshiyuki Yamashita, Shohei Morishima, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita:
Low-capture-power test generation for scan-based at-speed testing. ITC 2005: 10 - [c44]Lei Li, Krishnendu Chakrabarty, Seiji Kajihara, Shivakumar Swaminathan:
Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores. VLSI Design 2005: 53-58 - [c43]Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita:
On Low-Capture-Power Test Generation for Scan Testing. VTS 2005: 265-270 - 2004
- [j16]Seiji Kajihara, Kenjiro Taniguchi, Kohei Miyase, Irith Pomeranz, Sudhakar M. Reddy:
Don't Care Identification and Statistical Encoding for Test Data Compression. IEICE Trans. Inf. Syst. 87-D(3): 544-550 (2004) - [j15]Kohei Miyase, Seiji Kajihara:
XID: Don't care identification of test patterns for combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(2): 321-326 (2004) - [c42]Yoshinobu Higami, Seiji Kajihara, Shin-ya Kobayashi, Yuzo Takamatsu:
Techniques for Finding Xs in Test Sequences for Sequential Circuits and Applications to Test Length/Power Reduction. Asian Test Symposium 2004: 46-49 - [c41]Kohei Miyase, Seiji Kajihara, Sudhakar M. Reddy:
Multiple Scan Tree Design with Test Vector Modification. Asian Test Symposium 2004: 76-81 - [c40]Seiji Kajihara, Kewal K. Saluja, Sudhakar M. Reddy:
Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values. ETS 2004: 108-113 - [c39]Xiaoqing Wen, Tokiharu Miyoshi, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita:
On per-test fault diagnosis using the X-fault model. ICCAD 2004: 633-640 - [c38]Dong Hyun Baik, Kewal K. Saluja, Seiji Kajihara:
Random Access Scan: A solution to test power, test data volume and test time. VLSI Design 2004: 883-888 - 2003
- [j14]Yun Shao, Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara:
On Selecting Testable Paths in Scan Designs. J. Electron. Test. 19(4): 447-456 (2003) - [j13]Masayasu Fukunaga, Seiji Kajihara, Sadami Takeoka, Shinichi Yoshimura:
Evaluation of Delay Testing Based on Path Selection. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3208-3210 (2003) - [j12]Takeshi Asakawa, Kazuhiko Iwasaki, Seiji Kajihara:
BIST-oriented test pattern generator for detection of transition faults. Syst. Comput. Jpn. 34(3): 76-84 (2003) - [j11]Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz:
On test data volume reduction for multiple scan chain designs. ACM Trans. Design Autom. Electr. Syst. 8(4): 460-469 (2003) - [c37]Masayasu Fukunaga, Seiji Kajihara, Sadami Takeoka, Shinichi Yosimura:
On effective criterion of path selection for delay testing. ASP-DAC 2003: 757-762 - [c36]Masayasu Fukunaga, Seiji Kajihara, Sadami Takeoka:
On Estimation of Fault Efficiency for Path Delay Faults. Asian Test Symposium 2003: 64-67 - [c35]Kohei Miyase, Seiji Kajihara:
Optimal Scan Tree Construction with Test Vector Modification for Test Compression. Asian Test Symposium 2003: 136-141 - [c34]Seiji Kajihara, Yasumi Doi, Lei Li, Krishnendu Chakrabarty:
On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume. ICCD 2003: 387-396 - [c33]Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu, Seiji Kajihara, Irith Pomeranz:
A Method to Find Don't Care Values in Test Sequences for Sequential Circuits. ICCD 2003: 397- - 2002
- [c32]Seiji Kajihara, Kenjiro Taniguchi, Kohei Miyase, Irith Pomeranz, Sudhakar M. Reddy:
Test Data Compression Using Don?t-Care Identification and Statistical Encoding. Asian Test Symposium 2002: 67- - [c31]Kohei Miyase, Seiji Kajihara, Sudhakar M. Reddy:
A Method of Static Test Compaction Based on Don't Care Identification. DELTA 2002: 392-395 - [c30]Seiji Kajihara, Kenjiro Taniguchi, Irith Pomeranz, Sudhakar M. Reddy:
Test Data Compression Using Don't-Care Identification and Statistical Encoding. DELTA 2002: 413-416 - [c29]Yun Shao, Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara:
On selecting testable paths in scan designs. ETW 2002: 53-58 - [c28]Kohei Miyase, Seiji Kajihara, Irith Pomeranz, Sudhakar M. Reddy:
Don't-Care Identification on Specific Bits of Test Patterns. ICCD 2002: 194-199 - [c27]Sudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita:
On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout. ITC 2002: 83-89 - [c26]Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz:
On Test Data Volume Reduction for Multiple Scan Chain Designs. VTS 2002: 103-110 - [c25]Seiji Kajihara, Koji Ishida, Kohei Miyase:
Test Vector Modification for Power Reduction during Scan Testing. VTS 2002: 160-165 - 2001
- [c24]Yun Shao, Sudhakar M. Reddy, Seiji Kajihara, Irith Pomeranz:
An Efficient Method to Identify Untestable Path Delay Faults. Asian Test Symposium 2001: 233-238 - [c23]Kenichi Ichino, Takeshi Asakawa, Satoshi Fukumoto, Kazuhiko Iwasaki, Seiji Kajihara:
Hybrid BIST Using Partially Rotational Scan. Asian Test Symposium 2001: 379-384 - [c22]Seiji Kajihara, Kohei Miyase:
On Identifying Don't Care Inputs of Test Patterns for Combinational Circuits. ICCAD 2001: 364-369 - 2000
- [c21]Seiji Kajihara, Takashi Shimono, Irith Pomeranz, Sudhakar M. Reddy:
Enhanced untestable path analysis using edge graphs. Asian Test Symposium 2000: 139-144 - [c20]Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara, Atsushi Murakami, Sadami Takeoka, Mitsuyasu Ohta:
On validating data hold times for flip-flops in sequential circuits. ITC 2000: 317-325 - [c19]Atsushi Murakami, Seiji Kajihara, Tsutomu Sasao, Irith Pomeranz, Sudhakar M. Reddy:
Selection of potentially testable path delay faults for test generation. ITC 2000: 376-384
1990 – 1999
- 1999
- [c18]Seiji Kajihara, Atsushi Murakami, Tomohisa Kaneko:
On Compact Test Sets for Multiple Stuck-at Faults for Large Circuits. Asian Test Symposium 1999: 20-24 - [c17]Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara:
On an Effective Selection of IDDQ Measurement Vectors for Sequential Circuits. Asian Test Symposium 1999: 147-152 - [c16]Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara:
On Test Generation with A Limited Number of Tests. Great Lakes Symposium on VLSI 1999: 12-15 - 1998
- [c15]Hideyuki Ichihara, Seiji Kajihara, Kozo Kinoshita:
An Efficient Procedure for Obtaining Implication Relations and Its Application to Redundancy Identification. Asian Test Symposium 1998: 58-63 - [c14]Seiji Kajihara, Kewal K. Saluja:
On Test Pattern Compaction Using Random Pattern Fault Simulation. VLSI Design 1998: 464-469 - 1997
- [j10]Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita:
Synthesis of Sequential Circuits by Redundancy Removal and Retiming. J. Electron. Test. 11(1): 81-92 (1997) - [j9]Atsushi Yoshikawa, Seiji Kajihara, Masahiro Numa, Kozo Kinoshita:
A diagnosis method for single logic design errors in gate-level combinational circuits. Syst. Comput. Jpn. 28(6): 30-39 (1997) - [j8]Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara:
On invariant implication relations for removing partial circuits. Syst. Comput. Jpn. 28(7): 39-47 (1997) - [j7]Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara:
Compact test sets for high defect coverage. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(8): 923-930 (1997) - [c13]Seiji Kajihara, Tsutomu Sasao:
On the Adders with Minimum Tests. Asian Test Symposium 1997: 10-15 - [c12]Seiji Kajihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy:
A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths. VLSI Design 1997: 82-87 - 1996
- [c11]Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita:
Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique. Asian Test Symposium 1996: 94-99 - [c10]Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara:
On the effects of test compaction on defect coverage. VTS 1996: 430-437 - 1995
- [j6]Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita:
Partial scan design and test sequence generation based on reduced scan shift method. J. Electron. Test. 7(1-2): 115-124 (1995) - [j5]Seiji Kajihara, Rikiya Nishigaya, Tetsuji Sumioka, Kozo Kinoshita:
Acceleration Techniques of Multiple Fault Test Generation Using Vector Pair Analysis. IEICE Trans. Inf. Syst. 78-D(7): 811-816 (1995) - [j4]Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita:
Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement. IEICE Trans. Inf. Syst. 78-D(7): 861-867 (1995) - [j3]Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy:
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12): 1496-1504 (1995) - [c9]Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita:
Test sequence compaction by reduced scan shift and retiming. Asian Test Symposium 1995: 169-175 - [c8]Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita:
Synthesis for Testability by Sequential Redundancy Removal Using Retiming. FTCS 1995: 33-40 - [c7]Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita:
Resynthesis for sequential circuits designed with a specified initial state. VTS 1995: 152-157 - [c6]Remata S. Reddy, Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara:
Compact test generation for bridging faults under IDDQ testing. VTS 1995: 310-316 - 1994
- [c5]Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita:
Reduced Scan Shift: A New Testing Method for Sequential Circuit. ITC 1994: 624-630 - [c4]Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy:
On compacting test sets by addition and removal of test vectors. VTS 1994: 202-207 - 1993
- [j2]Seiji Kajihara, Kozo Kinoshita, Haruko Shiba:
Removal of redundancy in combinational circuits under classification of undetectable faults. Syst. Comput. Jpn. 24(7): 31-40 (1993) - [c3]Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy:
Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits. DAC 1993: 102-106 - [c2]Seiji Kajihara, Tetsuji Sumioka, Kozo Kinoshita:
Test generation for multiple faults based on parallel vector pair analysis. ICCAD 1993: 436-439 - 1992
- [c1]Seiji Kajihara, Haruko Shiba, Kozo Kinoshita:
Removal of Redundancy in Logic Circuits under Classification of Undetectable Faults. FTCS 1992: 263-270 - 1991
- [j1]Seiji Kajihara, Noriyoshi Itazaki, Kozo Kinoshita:
Stuck-open faults test generation for cmos combinational circuits. Syst. Comput. Jpn. 22(9): 33-42 (1991)
Coauthor Index
[c108] [c107] [j50] [c100] [c96] [c94] [c93] [j47] [c89] [c88] [j44] [j43] [j42] [j41] [c82] [c80] [c79] [c78] [c75] [c74] [j39] [j38] [c72] [c71] [c69] [c68] [c67] [j35] [j34] [j33] [j32] [c66] [c64] [c63] [c62] [j31] [j29] [j28] [c61] [c60] [c59] [c58] [j25] [c57] [c55] [j21] [c53] [c51] [j18] [c48] [j16] [j15] [c41] [j11] [c35] [c32] [c31] [c28] [c26] [c25] [c22]
[c107] [j50] [j49] [c100] [c96] [c94] [c93] [j47] [c91] [c90] [c89] [c88] [j44] [j43] [j42] [c83] [c82] [c80] [c75] [c74] [j39] [j38] [c72] [c71] [c69] [c68] [c67] [j35] [j34] [j33] [j32] [c66] [c64] [c63] [c62] [j31] [j29] [j28] [j27] [j26] [c61] [c60] [c59] [c58] [j25] [c57] [c56] [c55] [j23] [j21] [c54] [c53] [c52] [c51] [j20] [j18] [c50] [c48] [c47] [c45] [c43] [c39]
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-23 20:35 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
