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ORCIDVignesh Adhinarayanan
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2020 – today
- 2023
[c15]Gabriel H. Loh
, Michael J. Schulte, Mike Ignatowski, Vignesh Adhinarayanan, Shaizeen Aga, Derrick Aguren, Varun Agrawal, Ashwin M. Aji, Johnathan Alsop, Paul T. Bauman, Bradford M. Beckmann, Majed Valad Beigi, Sergey Blagodurov, Travis Boraten, Michael Boyer, William C. Brantley, Noel Chalmers, Shaoming Chen, Kevin Cheng, Michael L. Chu, David Cownie, Nicholas Curtis, Joris Del Pino, Nam Duong, Alexandru Dutu, Yasuko Eckert, Christopher Erb, Chip Freitag, Joseph L. Greathouse, Sudhanva Gurumurthi, Anthony Gutierrez, Khaled Hamidouche, Sachin Hossamani, Wei Huang, Mahzabeen Islam, Nuwan Jayasena, John Kalamatianos, Onur Kayiran, Jagadish Kotra, Alan Lee, Daniel Lowell, Niti Madan, Abhinandan Majumdar, Nicholas Malaya, Srilatha Manne, Susumu Mashimo, Damon McDougall, Elliot Mednick, Michael Mishkin, Mark Nutter, Indrani Paul, Matthew Poremba, Brandon Potter, Kishore Punniyamurthy, Sooraj Puthoor, Steven E. Raasch, Karthik Rao, Gregory Rodgers, Marko Scrbak, Mohammad Seyedzadeh, John Slice, Vilas Sridharan, René van Oostrum, Eric Van Tassell, Abhinav Vishnu, Samuel Wasmundt, Mark Wilkening, Noah Wolfe, Mark Wyse, Adithya Yalavarti, Dmitri Yudanov:
A Research Retrospective on AMD's Exascale Computing Journey. ISCA 2023: 81:1-81:14- 2020
- [c14]Vignesh Adhinarayanan, Wu-chun Feng:
Approximate Pattern Matching for On-Chip Interconnect Traffic Prediction. PACT 2020: 357-358 - [c13]Gregory D. Abram, Vignesh Adhinarayanan, Wu-chun Feng, David H. Rogers, James P. Ahrens:
ETH: An Architecture for Exploring the Design Space of In-situ Scientific Visualization. IPDPS 2020: 515-526
2010 – 2019
- 2018
- [c12]Bishwajit Dutta, Vignesh Adhinarayanan, Wu-chun Feng:
GPU power prediction via ensemble machine learning for DVFS space exploration. CF 2018: 240-243 - [c11]Vignesh Adhinarayanan, Bishwajit Dutta, Wu-chun Feng:
Making a Case for Green High-Performance Visualization Via Embedded Graphics Processors. IPDPS Workshops 2018: 721-724 - 2017
- [c10]Vignesh Adhinarayanan, Wu-chun Feng, David H. Rogers, James P. Ahrens, Scott Pakin:
Characterizing and Modeling Power and Energy for Extreme-Scale In-Situ Visualization. IPDPS 2017: 978-987 - 2016
- [c9]Vignesh Adhinarayanan, Balaji Subramaniam, Wu-chun Feng:
Online Power Estimation of Graphics Processing Units. CCGrid 2016: 245-254 - [c8]Vignesh Adhinarayanan, Indrani Paul, Joseph L. Greathouse, Wei Huang, Ashutosh Pattnaik, Wu-chun Feng:
Measuring and modeling on-chip interconnect power on real hardware. IISWC 2016: 23-33 - [c7]Vignesh Adhinarayanan, Wu-chun Feng:
An automated framework for characterizing and subsetting GPGPU workloads. ISPASS 2016: 307-317 - 2015
- [c6]Vignesh Adhinarayanan, Wu-chun Feng, Jonathan Woodring, David H. Rogers, James P. Ahrens:
On the Greenness of In-Situ and Post-Processing Visualization Pipelines. IPDPS Workshops 2015: 880-887 - 2014
- [c5]Vignesh Adhinarayanan, Thaddeus Koehn, Krzysztof Kepa, Wu-chun Feng, Peter Athanas:
On the performance and energy efficiency of FPGAs and GPUs for polyphase channelization. ReConFig 2014: 1-7 - 2013
- [c4]Carlo C. del Mundo, Vignesh Adhinarayanan, Wu-chun Feng:
Accelerating fast Fourier Transform for wideband channelization. ICC 2013: 4776-4780 - [c3]Vignesh Adhinarayanan, Wu-chun Feng:
Wideband Channelization for Software-Defined Radio via Mobile Graphics Processors. ICPADS 2013: 86-93 - 2012
- [c2]Nagarajan Venkateswaran, Rajagopal Hariharan, Vinesh Srinivasan, Ram Srivatsa Kannan, Prashanth Thinakaran, Vigneshwaran Sankaran, Bharanidharan Vasudevan, Ravindhiran Mukundrajan, Nachiappan Chidambaram Nachiappan, Aswin Sridharan, Karthikeyan P. Saravanan, Vignesh Adhinarayanan, Vignesh Veppur Sankaranarayanan:
SCOC IP Cores for Custom Built Supercomputing Nodes. ISVLSI 2012: 255-260 - [c1]Nagarajan Venkateswaran, Vinesh Srinivasan, Ram Srivatsa Kannan, Prashanth Thinakaran, Rajagopal Hariharan, Bharanidharan Vasudevan, Nachiappan Chidambaram Nachiappan, Karthikeyan P. Saravanan, Aswin Sridharan, Vigneshwaran Sankaran, Vignesh Adhinarayanan, V. S. Vignesh, Ravindhiran Mukundrajan:
Compilation Accelerator on Silicon. ISVLSI 2012: 267-272
Coauthor Index
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