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2010 – 2019
- 2015
[j6]Kaushik Roy, Deliang Fan, Xuanyao Fong
, Yusung Kim, Mrigank Sharad, Somnath Paul, Subho Chatterjee, Swarup Bhunia, Saibal Mukhopadhyay:
Exploring Spin Transfer Torque Devices for Unconventional Computing. IEEE J. Emerg. Sel. Topics Circuits Syst. 5(1): 5-16 (2015)- [j5]Wen Yueh, Subho Chatterjee, Muneeb Zia, Swarup Bhunia, Saibal Mukhopadhyay:
A Memory-Based Logic Block With Optimized-for-Read SRAM for Energy-Efficient Reconfigurable Computing Fabric. IEEE Trans. Circuits Syst. II Express Briefs 62-II(6): 593-597 (2015) - 2014
- [c9]Subho Chatterjee, Pramod Kolar, Wei Jian Chan, Jae Y. Ko, Gunjan H. Pandya:
A methodology for yield-specific leakage estimation in memory. CICC 2014: 1-4 - 2013
- [j4]Subho Chatterjee, Sayeef S. Salahuddin, Satish Kumar, Saibal Mukhopadhyay:
Electrothermal analysis of spin-transfer-torque random access memory arrays. ACM J. Emerg. Technol. Comput. Syst. 9(2): 15:1-15:17 (2013) - 2012
- [b1]Subho Chatterjee:
A design methodology for robust, energy-efficient, application-aware memory systems. Georgia Institute of Technology, Atlanta, GA, USA, 2012 - [c8]Wen Yueh, Subho Chatterjee, Amit Ranjan Trivedi, Saibal Mukhopadhyay:
On the parametric failures of SRAM in a 3D-die stack considering tier-to-tier supply cross-talk. VTS 2012: 264-269 - 2011
- [j3]Somnath Paul, Subho Chatterjee, Saibal Mukhopadhyay, Swarup Bhunia:
Energy-Efficient Reconfigurable Computing Using a Circuit-Architecture-Software Co-Design Approach. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(3): 369-380 (2011) - [j2]Subho Chatterjee, Mitchelle Rasquinha, Sudhakar Yalamanchili, Saibal Mukhopadhyay:
A Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective. IEEE Trans. Very Large Scale Integr. Syst. 19(5): 809-817 (2011) - [c7]Aritra Banerjee, Subho Chatterjee, Azad Naeemi, Abhijit Chatterjee:
Power Aware Post-manufacture Tuning of Analog Nanocircuits. ETS 2011: 57-62 - 2010
- [j1]Subho Chatterjee, Sayeef S. Salahuddin, Saibal Mukhopadhyay:
Dual-Source-Line-Bias Scheme to Improve the Read Margin and Sensing Accuracy of STTRAM in Sub-90-nm Nodes. IEEE Trans. Circuits Syst. II Express Briefs 57-II(3): 208-212 (2010) - [c6]Subho Chatterjee, Sayeef S. Salahuddin, Satish Kumar, Saibal Mukhopadhyay:
Analysis of thermal behaviors of spin-torque-transfer RAM: a simulation study. ISLPED 2010: 13-18 - [c5]Mitchelle Rasquinha, Dhruv Choudhary, Subho Chatterjee, Saibal Mukhopadhyay, Sudhakar Yalamanchili:
An energy efficient cache design using spin torque transfer (STT) RAM. ISLPED 2010: 389-394
2000 – 2009
- 2009
- [c4]Somnath Paul, Subho Chatterjee, Saibal Mukhopadhyay, Swarup Bhunia:
A circuit-software co-design approach for improving EDP in reconfigurable frameworks. ICCAD 2009: 109-112 - [c3]Subho Chatterjee, Mitchelle Rasquinha, Sudhakar Yalamanchili, Saibal Mukhopadhyay:
A methodology for robust, energy efficient design of Spin-Torque-Transfer RAM arrays at scaled technologies. ICCAD 2009: 474-477 - 2008
- [c2]Amitava Banerjee, Subho Chatterjee, Amit Patra, Siddhartha Mukhopadhyay:
An efficient approach to model distortion in weakly nonlinear Gm - C filters. ISCAS 2008: 1312-1315 - [c1]Amal Kumar Kundu, Subho Chatterjee, Tarun Kanti Bhattacharyya:
A Fast Settling 100dB OPAMP in 180nm CMOS Process with Compensation Based Optimisation. VLSI Design 2008: 311-316
Coauthor Index
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