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2020 – today
- 2023
[j9]Bo Ding
, Jinglei Huang, Qi Xu, Junpeng Wang, Song Chen, Yi Kang:
Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems. ACM Trans. Design Autom. Electr. Syst. 28(1): 7:1-7:21 (2023)- [j8]Bo Ding, Jinglei Huang, Junpeng Wang, Qi Xu, Song Chen, Yi Kang:
Task Modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems with Heterogeneous Resources. ACM Trans. Design Autom. Electr. Syst. 28(6): 103:1-103:26 (2023) - 2022
- [j7]Mengke Ge, Xiaobing Ni, Qi Xu, Song Chen, Jinglei Huang, Yi Kang, Feng Wu:
Synthesizing Brain-network-inspired Interconnections for Large-scale Network-on-chips. ACM Trans. Design Autom. Electr. Syst. 27(1): 9:1-9:30 (2022) - [i4]Bo Ding, Jinglei Huang, Junpeng Wang, Qi Xu, Song Chen, Yi Kang:
Task modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems Based on Modern Heterogeneous FPGAs. CoRR abs/2212.05397 (2022) - 2021
- [j6]Jing Tian, Xinchang Hao, Jibo Huang, Jinglei Huang, Mitsuo Gen:
Solving slot allocation problem with multiple ATFM measures by using enhanced meta-heuristic algorithm. Comput. Ind. Eng. 160: 107602 (2021) - [i3]Mengke Ge, Xiaobing Ni, Qi Xu, Song Chen, Jinglei Huang, Yi Kang, Feng Wu:
Synthesizing Brain-Network-Inspired Interconnections for Large-Scale Network-on-Chips. CoRR abs/2108.01298 (2021) - 2020
- [j5]Song Chen, Jinglei Huang, Xiaodong Xu, Bo Ding, Qi Xu:
Integrated Optimization of Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(1): 199-212 (2020) - [j4]Song Chen, Mengke Ge, Zhigang Li, Jinglei Huang, Qi Xu, Feng Wu:
Generalized Fault-Tolerance Topology Generation for Application-Specific Network-on-Chips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(6): 1191-1204 (2020)
2010 – 2019
- 2019
- [j3]Jinglei Huang, Xiaodong Xu, Nan Wang, Song Chen:
Reconfigurable topology synthesis for application-specific NoC on partially dynamically reconfigurable systems. Integr. 65: 331-343 (2019) - [i2]Song Chen, Mengke Ge, Zhigang Li, Jinglei Huang, Qi Xu, Feng Wu:
Generalized Fault-Tolerance Topology Generation for Application Specific Network-on-Chips. CoRR abs/1908.00165 (2019) - 2018
- [j2]Jinglei Huang, Wei Zhong, Zhigang Li, Song Chen:
Lagrangian relaxation-based routing path allocation for application-specific network-on-chips. Integr. 61: 20-28 (2018) - [i1]Song Chen, Jinglei Huang, Xiaodong Xu, Qi Xu:
Integrated Optimization of Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems. CoRR abs/1803.03748 (2018) - 2017
- [c4]Zhigang Li, Jinglei Huang, Qi Xu, Song Chen:
Integer linear programming based fault-tolerant topology synthesis for application-specific NoC. ASICON 2017: 96-99 - [c3]Xiaodong Xu, Qi Xu, Jinglei Huang, Song Chen:
An Integrated Optimization Framework for Partitioning, Scheduling and Floorplanning on Partially Dynamically Reconfigurable FPGAs. ACM Great Lakes Symposium on VLSI 2017: 403-406 - [c2]Jinglei Huang, Xiaodong Xu, Lan Yao, Song Chen:
Reconfigurable topology synthesis for application-specific noc on partially dynamically reconfigurable FPGAs. SLIP 2017: 1-8 - 2016
- [j1]Jinglei Huang, Song Chen, Wei Zhong, Wenchao Zhang, Shengxi Diao, Fujiang Lin:
Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips with RF-Interconnect. ACM Trans. Design Autom. Electr. Syst. 21(3): 40:1-40:23 (2016) - 2015
- [c1]Jinglei Huang, Zhigang Li, Wei Zhong, Song Chen:
Lagrangian relaxation based topology synthesis for Application-Specific Network-on-Chips. ASICON 2015: 1-4
Coauthor Index
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