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ORCIDACM Transactions on Design Automation of Electronic Systems, Volume 28
Volume 28, Number 1, January 2023
- José Romero Hung
, Chao Li, Taolei Wang, Jinyang Guo, Pengyu Wang, Chuanming Shao, Jing Wang, Guoyong Shi, Xiangwen Liu, Hanqing Wu:
DRAGON: Dynamic Recurrent Accelerator for Graph Online Convolution. 1:1-1:27 - Svetlana Minakova, Todor P. Stefanov:
Memory-Throughput Trade-off for CNN-Based Applications at the Edge. 2:1-2:26 - Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar:
Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks. 3:1-3:27 - Jan Spieck, Stefan Wildermann, Jürgen Teich:
A Learning-based Methodology for Scenario-aware Mapping of Soft Real-time Applications onto Heterogeneous MPSoCs. 4:1-4:40 - Chunqiao Li, Chengtao An, Fan Yang, Xuan Zeng:
ESPSim: An Efficient Scalable Power Grid Simulator Based on Parallel Algebraic Multigrid. 5:1-5:31 - Chenglong Huang, Nuo Xu, Junwei Zeng, Wenqing Wang, Yihong Hu, Liang Fang, Desheng Ma, Yanting Chen:
Rescuing ReRAM-based Neural Computing Systems from Device Variation. 6:1-6:17 - Bo Ding, Jinglei Huang, Qi Xu, Junpeng Wang, Song Chen, Yi Kang:
Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems. 7:1-7:21 - Junwei Zeng, Nuo Xu, Yabo Chen, Chenglong Huang, Zhiwei Li, Liang Fang:
AIMCU-MESO: An In-Memory Computing Unit Constructed by MESO Device. 8:1-8:16 - Sourav Das, Sayandeep Sanyal, Aritra Hazra, Pallab Dasgupta:
CoVerPlan: A Comprehensive Verification Planning Framework Leveraging PSS Specifications. 9:1-9:32 - Zhuoran Song, Naifeng Jing, Xiaoyao Liang:
E2-VOR: An End-to-End En/Decoder Architecture for Efficient Video Object Recognition. 10:1-10:21 - Zhiqiang Zhao, Zhuo Feng:
A Multilevel Spectral Framework for Scalable Vectorless Power/Thermal Integrity Verification. 11:1-11:25 - Kai Huang, Bowen Li, Dongliang Xiong, Haitian Jiang, Xiaowen Jiang, Xiaolang Yan, Luc Claesen, Dehong Liu, Junjian Chen, Zhili Liu:
Structured Dynamic Precision for Deep Neural Networks Quantization. 12:1-12:24 - Farhad Ebrahimi-Azandaryani, Omid Akbari, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram:
Accuracy Configurable Adders with Negligible Delay Overhead in Exact Operating Mode. 13:1-13:14
Volume 28, Number 2, March 2023
- Yibo Lin, Avi Ziv, Haoxing Ren:
Introduction to the Special Issue on Machine Learning for CAD/EDA. 14:1-14:2 - Daniela Sánchez, Lorenzo Servadei, Gamze Naz Kiprit, Robert Wille, Wolfgang Ecker:
A Comprehensive Survey on Electronic Design Automation and Graph Neural Networks: Theory and Applications. 15:1-15:27 - David Selasi Koblah, Rabin Yu Acharya, Daniel E. Capecci, Olivia P. Dizon-Paradis, Shahin Tajik, Fatemeh Ganji, Damon L. Woodard, Domenic Forte:
A Survey and Perspective on Artificial Intelligence for Security-Aware Electronic Design Automation. 16:1-16:57 - Shaoze Fan, Shun Zhang, Jianbo Liu, Ningyuan Cao, Xiaoxiao Guo, Jing Li, Xin Zhang:
Power Converter Circuit Design Automation Using Parallel Monte Carlo Tree Search. 17:1-17:33 - Ling-Yen Song, Chih-Yun Chou, Tung-Chieh Kuo, Chien-Nan Liu, Juinn-Dar Huang:
Machine Learning Assisted Circuit Sizing Approach for Low-Voltage Analog Circuits with Efficient Variation-Aware Optimization. 18:1-18:22 - Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu:
Performance-driven Wire Sizing for Analog Integrated Circuits. 19:1-19:23 - Jiawen Cheng, Yong Xiao, Yun Shao, Guanghai Dong, Songlin Lyu, Wenjian Yu:
Machine-learning-driven Architectural Selection of Adders and Multipliers in Logic Synthesis. 20:1-20:16 - Yiting Liu, Ziyi Ju, Zhengming Li, Mingzhi Dong, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang:
GraphPlanner: Floorplanning with Graph Neural Network. 21:1-21:24 - Chenlei Fang, Qicheng Huang, Zeye Liu, Ruizhou Ding, Ronald D. Blanton:
Efficient Test Chip Design via Smart Computation. 22:1-22:31 - Erika Susana Alcorta Lozano, Andreas Gerstlauer:
Learning-based Phase-aware Multi-core CPU Workload Forecasting. 23:1-23:27 - Benzheng Li, Xi Zhang, Hailong You, Zhongdong Qi, Yuming Zhang:
Machine Learning Based Framework for Fast Resource Estimation of RTL Designs Targeting FPGAs. 24:1-24:16 - Lorenzo Ferretti, Andrea Cini, Georgios Zacharopoulos, Cesare Alippi, Laura Pozzi:
Graph Neural Networks for High-Level Synthesis Design Space Exploration. 25:1-25:20 - Felix Last, Ulf Schlichtmann:
Training PPA Models for Embedded Memories on a Low-data Diet. 26:1-26:24 - Wei W. Xing, Xiang Jin, Tian Feng, Dan Niu, Weisheng Zhao, Zhou Jin:
BoA-PTA: A Bayesian Optimization Accelerated PTA Solver for SPICE Simulation. 27:1-27:26 - Ruochen Dai, Tuba Yavuz:
A Symbolic Approach to Detecting Hardware Trojans Triggered by Don't Care Transitions. 28:1-28:31 - Zhisheng Chen, Wenzhong Guo, Genggeng Liu, Xing Huang:
Application Mapping and Control-system Design for Microfluidic Biochips with Distributed Channel Storage. 29:1-29:30
Volume 28, Number 3, May 2023
- Dwaipayan Choudhury, Lizhi Xiang, Aravind Sukumaran-Rajam, Anantharaman Kalyanaraman, Partha Pratim Pande:
Accelerating Graph Computations on 3D NoC-Enabled PIM Architectures. 30:1-30:16 - Jayoung Lee, Pengcheng Wang, Ran Xu, Sarthak Jain, Venkat Dasari, Noah Weston, Yin Li, Saurabh Bagchi, Somali Chaterji:
Virtuoso: Energy- and Latency-aware Streamlining of Streaming Videos on Systems-on-Chips. 31:1-31:32 - Ashish Reddy Bommana, Susheel Ujwal Siddamshetty, Pudi Dhilleswararao, Arvind Thumatti K. R., Srinivas Boppu, M. Sabarimalai Manikandan, Linga Reddy Cenkeramaddi:
Design of Synthesis-time Vectorized Arithmetic Hardware for Tapered Floating-point Addition and Subtraction. 32:1-32:35 - Chun-Chieh Yang, Yi-Ru Chen, Hui-Hsin Liao, Yuan-Ming Chang, Jenq-Kuen Lee:
Auto-tuning Fixed-point Precision with TVM on RISC-V Packed SIMD Extension. 33:1-33:21 - Shanshi Huang, Hongwu Jiang, Shimeng Yu:
Hardware-aware Quantization/Mapping Strategies for Compute-in-Memory Accelerators. 34:1-34:23 - Lang Feng, Wenjian Liu, Chuliang Guo, Ke Tang, Cheng Zhuo, Zhongfeng Wang:
GANDSE: Generative Adversarial Network-based Design Space Exploration for Neural Network Accelerator Design. 35:1-35:20 - Junpeng Wang, Haitao Du, Bo Ding, Qi Xu, Song Chen, Yi Kang:
DDAM: Data Distribution-Aware Mapping of CNNs on Processing-In-Memory Systems. 36:1-36:30 - Bhawna Rawat, Poornima Mittal:
A Switching NMOS Based Single Ended Sense Amplifier for High Density SRAM Applications. 37:1-37:14 - Danny Pereira, Anirban Ghose, Sumana Ghosh, Soumyajit Dey:
Inferencing on Edge Devices: A Time- and Space-aware Co-scheduling Approach. 38:1-38:33 - Yanze Huang, Kui Wen, Limei Lin, Li Xu, Sun-Yuan Hsieh:
Component Fault Diagnosability of Hierarchical Cubic Networks. 39:1-39:19 - Qi Nie, Sharad Malik:
CNNFlow: Memory-driven Data Flow Optimization for Convolutional Neural Networks. 40:1-40:36 - Ricardo Gonzalez de Oliveira, Nicolas Navet, Achim Henkel:
Multi-Objective Optimization for Safety-Related Available E/E Architectures Scoping Highly Automated Driving Vehicles. 41:1-41:37 - Mervat M. A. Mahmoud, Nahla E. Elashkar, Heba H. Draz:
Low-energy Pipelined Hardware Design for Approximate Medium Filter. 42:1-42:21 - Jordi Cardona, Carles Hernández, Jaume Abella, Enrico Mezzetti, Francisco J. Cazorla:
Accurately Measuring Contention in Mesh NoCs in Time-Sensitive Embedded Systems. 43:1-43:34 - Yajuan Du, Siyi Huang, Yao Zhou, Qiao Li:
Towards LDPC Read Performance of 3D Flash Memories with Layer-induced Error Characteristics. 44:1-44:25 - Yuhao Zhou, Zhenxue He, Jianhui Jiang, Jia Liu, Juncai He, Tao Wang, Limin Xiao, Xiang Wang:
Fast Area Optimization Approach for XNOR/OR-based Fixed Polarity Reed-Muller Logic Circuits based on Multi-strategy Wolf Pack Algorithm. 45:1-45:16 - Senling Wang, Xihong Zhou, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima:
Test Point Insertion for Multi-Cycle Power-On Self-Test. 46:1-46:21 - Trung Le, Zhao Zhang, Zhichun Zhu:
Polling-Based Memory Interface. 47:1-47:23
Volume 28, Number 4, July 2023
- Igor L. Markov, Fan Yang, Li Shang, Hai Zhou:
Guest Editor's Introduction: Machine Learning for VLSI Physical Design. 48:1-48:3 - Suhas Krishna Kashyap, Sule Ozev:
IMPRoVED: Integrated Method to Predict PostRouting setup Violations in Early Design Stages. 49:1-49:23 - Daijoon Hyun, Sunwha Koh, Younggwang Jung, Taeyoung Kim, Youngsoo Shin:
Routability Optimization of Extreme Aspect Ratio Design through Non-uniform Placement Utilization and Selective Flip-flop Stacking. 50:1-50:19 - Dmitry Utyamishev, Inna Partin-Vaisband:
Multiterminal Pathfinding in Practical VLSI Systems with Deep Neural Networks. 51:1-51:19 - Chung-Kuan Cheng, Chester Holtz, Andrew B. Kahng, Bill Lin, Uday Mallappa:
DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs. 52:1-52:31 - Ping-Wei Huang, Yao-Wen Chang:
Routability-driven Power/Ground Network Optimization Based on Machine Learning. 53:1-53:27 - Xiao Dong, Yufei Chen, Jun Chen, Yucheng Wang, Ji Li, Tianming Ni, Zhiguo Shi, Xunzhao Yin, Cheng Zhuo:
Worst-case Power Integrity Prediction Using Convolutional Neural Network. 54:1-54:19 - Yi-Chen Lu, Siddhartha Nath, Sai Pentapati, Sung Kyu Lim:
ECO-GNN: Signoff Power Prediction Using Graph Neural Networks with Subgraph Approximation. 55:1-55:22 - Dingcheng Yang, Haoyuan Li, Wenjian Yu, Yuanbo Guo, Wenjie Liang:
CNN-Cap: Effective Convolutional Neural Network-based Capacitance Models for Interconnect Capacitance Extraction. 56:1-56:22 - Tianshu Hou, Peining Zhen, Zhigang Ji, Hai-Bao Chen:
A Deep Learning Framework for Solving Stress-based Partial Differential Equations in Electromigration Analysis. 57:1-57:20 - Qing Zhang, Huajie Huang, Jizuo Li, Yuhang Zhang, Yongfu Li:
CmpCNN: CMP Modeling with Transfer Learning CNN Architecture. 58:1-58:18 - Ahmad O. Aseeri:
A Problem-tailored Adversarial Deep Neural Network-Based Attack Model for Feed-Forward Physical Unclonable Functions. 59:1-59:18
- Abhiroop Bhattacharjee, Priyadarshini Panda:
SwitchX: Gmin-Gmax Switching for Energy-efficient and Robust Implementation of Binarized Neural Networks on ReRAM Xbars. 60:1-60:21 - Po-Hsuan Huang, Chia-Heng Tu, Shen-Ming Chung, Pei-Yuan Wu, Tung-Lin Tsai, Yi-An Lin, Chun-Yi Dai, Tzu-Yi Liao:
SecureTVM: A TVM-based Compiler Framework for Selective Privacy-preserving Neural Inference. 61:1-61:28 - Abrar A. Ibrahim, Ahmed M. Y. Ibrahim, M. Watheq El-Kharashi, Mona Safar:
Optimal Pattern Retargeting in IEEE 1687 Networks: A SAT-based Upper-Bound Computation. 62:1-62:26 - Bruno Ferres, Olivier Muller, Frédéric Rousseau:
A Chisel Framework for Flexible Design Space Exploration through a Functional Approach. 63:1-63:31 - Muhammad Imran Khan:
Harmonic Estimation and Comparative Analysis of Ultra-High Speed Flip-Flop and Latch Topologies for Low Power and High Performance Future Generation Micro-/Nano Electronic Systems. 64:1-64:17 - Xu He, Yao Wang, Chang Liu, Qiang Wu, Juan Luo, Yang Guo:
A Soft-Error Mitigation Approach Using Pulse Quenching Enhancement at Detailed Placement for Combinational Circuits. 65:1-65:22 - Reza Kazerooni-Zand, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram:
Memristive-based Mixed-signal CGRA for Accelerating Deep Neural Network Inference. 66:1-66:25 - Cheng Chu, Cheng Liu, Dawen Xu, Ying Wang, Tao Luo, Huawei Li, Xiaowei Li:
Accelerating Deformable Convolution Networks with Dynamic and Irregular Memory Accesses. 67:1-67:23
Volume 28, Number 5, September 2023
- Iris Hui-Ru Jiang, David G. Chinnery, Gracieli Posser, Jens Lienig:
Introduction to the Special Section on Advances in Physical Design Automation. 68:1-68:3 - Ramprasath Srinivasa Gopalakrishnan, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar:
A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts. 69:1-69:25 - Min Wei, Xingyu Tong, Yuan Wen, Jianli Chen, Jun Yu, Wenxing Zhu, Yao-Wen Chang:
Analytical Placement with 3D Poisson's Equation and ADMM-based Optimization for Large-scale 2.5D Heterogeneous FPGAs. 70:1-70:24 - Stefan Hougardy, Meike Neuwohner, Ulrike Schorr:
A Fast Optimal Double-row Legalization Algorithm. 71:1-71:26 - Siad Daboul, Stephan Held, Bento Natura, Daniel Rotter:
Global Interconnect Optimization. 72:1-72:24 - Zhonghua Zhou, Yuxuan Pan, Guy G. F. Lemieux, André Ivanov:
MEDUSA: A Multi-Resolution Machine Learning Congestion Estimation Method for 2D and 3D Global Routing. 73:1-73:25 - Su Zheng, Hao Geng, Chen Bai, Bei Yu, Martin D. F. Wong:
Boosting VLSI Design Flow Parameter Tuning with Random Embedding and Multi-objective Trust-region Bayesian Optimization. 74:1-74:23 - Gauthaman Murali, Anthony Agnesina, Sung Kyu Lim:
A PPA Study of Reinforced Placement Parameter Autotuning: Pseudo-3D vs. True-3D Placers. 75:1-75:22 - Pruek Vanna-Iampikul, Yi-Chen Lu, Da Eun Shim, Sung Kyu Lim:
GNN-based Multi-bit Flip-flop Clustering and Post-clustering Design Optimization for Energy-efficient 3D ICs. 76:1-76:26 - Jun-Sheng Wu, Chi-An Pan, Yi-Yu Liu:
ILP-based Substrate Routing with Mismatched Via Dimension Consideration for Wire-bonding FBGA Package Design. 77:1-77:26 - Yanjiang Liu, Junwei Li, Tongzhou Qu, Zibin Dai:
CBDC-PUF: A Novel Physical Unclonable Function Design Framework Utilizing Configurable Butterfly Delay Chain Against Modeling Attack. 78:1-78:17
- Erfan Aghaeekiasaraee, Aysa Fakheri Tabrizi, Tiago Augusto Fontana, Renan Netto, Sheiny Fabre Almeida, Upma Gandhi, José Luís Güntzel, David T. Westwick, Laleh Behjat:
CRP2.0: A Fast and Robust Cooperation between Routing and Placement in Advanced Technology Nodes. 79:1-79:42 - Binwu Zhu, Xinyun Zhang, Yibo Lin, Bei Yu, Martin D. F. Wong:
DRC-SG 2.0: Efficient Design Rule Checking Script Generation via Key Information Extraction. 80:1-80:18 - Angeliki Kritikakou, Stefanos Skalistis:
Mitigating Mode-switch through Run-time Computation of Response Time. 81:1-81:26 - Zilu Wang, Xinming Shi, Xin Yao:
A Brain-Inspired Hardware Architecture for Evolutionary Algorithms Based on Memristive Arrays. 82:1-82:32 - Mohammad Mezanur Rahman Monjur, Joshua Calzadillas, Qiaoyan Yu:
Hardware Security Risks and Threat Analyses in Advanced Manufacturing Industry. 83:1-83:22 - Gaurav Narang, Aryan Deshwal, Raid Ayoub, Michael Kishinevsky, Janardhan Rao Doppa, Partha Pratim Pande:
Dynamic Power Management in Large Manycore Systems: A Learning-to-Search Framework. 84:1-84:21 - Jingweijia Tan, Weiren Wang, Maodi Ma, Xiaohui Wei, Kaige Yan:
Improving the Performance of CNN Accelerator Architecture under the Impact of Process Variations. 85:1-85:21 - Meng-Jing Li, Yu-Chuan Yen, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang:
A Constructive Approach for Threshold Function Identification. 86:1-86:19 - Nuzhat Yamin, Ganapati Bhat:
Uncertainty-aware Energy Harvest Prediction and Management for IoT Devices. 87:1-87:33
Volume 28, Number 6, November 2023
- Ruisi Zhang, Shehzeen Hussain, Huili Chen, Mojan Javaheripi, Farinaz Koushanfar:
Systemization of Knowledge: Robust Deep Learning using Hardware-software co-design in Centralized and Federated Settings. 88:1-88:32
- Huaixi Lu, Yue Xing, Aarti Gupta, Sharad Malik:
SoC Protocol Implementation Verification Using Instruction-Level Abstraction Specifications. 89:1-89:24 - Xu He, Yao Wang, Zhiyong Fu, Yipei Wang, Yang Guo:
A General Layout Pattern Clustering Using Geometric Matching-based Clip Relocation and Lower-bound Aided Optimization. 90:1-90:23 - Yajing Chang, Yingjian Yan, Chunsheng Zhu, Yanjiang Liu:
A High-performance Masking Design Approach for Saber against High-order Side-channel Attack. 91:1-91:19 - Stylianos I. Venieris, Javier Fernández-Marqués, Nicholas D. Lane:
Mitigating Memory Wall Effects in CNN Engines with On-the-Fly Weights Generation. 92:1-92:31 - Muhtadi Choudhury, Minyan Gao, Avinash Varna, Elad Peer, Domenic Forte:
Enhanced PATRON: Fault Injection and Power-aware FSM Encoding Through Linear Programming. 93:1-93:26 - Ayush Dahiya, Poornima Mittal, Rajesh Rohilla:
Modified Decoupled Sense Amplifier with Improved Sensing Speed for Low-Voltage Differential SRAM. 94:1-94:15 - Mahum Naseer, Osman Hasan, Muhammad Shafique:
QuanDA: GPU Accelerated Quantitative Deep Neural Network Analysis. 95:1-95:21 - Bhawna Rawat, Poornima Mittal:
A Reconfigurable 7T SRAM Bit Cell for High Speed, Power Saving and Low Voltage Application. 96:1-96:14 - S. Sivakumar, John Jose:
Self Adaptive Logical Split Cache Techniques for Delayed Aging of NVM LLC. 97:1-97:24 - Khalil Esper, Stefan Wildermann, Jürgen Teich:
Automatic Synthesis of FSMs for Enforcing Non-functional Requirements on MPSoCs Using Multi-objective Evolutionary Algorithms. 98:1-98:20 - Debabrata Senapati, Kousik Rajesh, Chandan Karfa, Arnab Sarkar:
TMDS: Temperature-aware Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems. 99:1-99:22 - Qinghui Hong, Richeng Huang, Pingdan Xiao, Jun Li, Jingru Sun, Jiliang Zhang:
Programmable In-memory Computing Circuit of Fast Hartley Transform. 100:1-100:23 - Debraj Kundu, Sudip Roy:
Multi-target Fluid Mixing in MEDA Biochips: Theory and an Attempt toward Waste Minimization. 101:1-101:26 - Shanglin Zhou, Mikhail A. Bragin, Deniz Gurevin, Lynn Pepin, Fei Miao, Caiwen Ding:
Surrogate Lagrangian Relaxation: A Path to Retrain-Free Deep Neural Network Pruning. 102:1-102:19 - Bo Ding, Jinglei Huang, Junpeng Wang, Qi Xu, Song Chen, Yi Kang:
Task Modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems with Heterogeneous Resources. 103:1-103:26 - Wenxiong Lin, Haojie Wu, Peng Gao, Wenjun Luo, Shuting Cai, Xiaoming Xiong:
Sequential Routing-based Time-division Multiplexing Optimization for Multi-FPGA Systems. 104:1-104:10 - Pushkar Praveen, R. K. Singh:
Design of Enhanced Reversible 9T SRAM Design for the Reduction in Sub-threshold Leakage Current with14nm FinFET Technology. 105:1-105:29
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