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2020 – today
- 2024
[c9]W. Kim, V. Pica
, N. Jossart, Farrukh Yasin, Kurt Wostyn, S. Couet, Sidharth Rao:
A novel test and analysis scheme to elucidate tail bit characteristics in STT-MRAM arrays. IMW 2024: 1-4- [c8]Farrukh Yasin, A. Palomino, A. Kumar, V. Pica, Simon Van Beek, Giacomo Talmelli, V. D. Nguyen, Stefan Cosemans, D. Crotti, Kurt Wostyn, Gouri Sankar Kar, Sebastien Couet:
Extremely Scaled Perpendicular SOT-MRAM Array Integration on 300mm Wafer. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c7]Siddharth Rao, Kaiming Cai, Giacomo Talmelli, Nathali Franchina-Vergel, Ward Janssens, Hubert Hody, Farrukh Yasin, Kurt Wostyn, Sebastien Couet:
Spin-orbit torque MRAM for ultrafast cache and neuromorphic computing applications. IMW 2023: 1-4 - 2021
- [c6]Sidharth Rao, Woojin Kim, Simon Van Beek, Shreya Kundu, Manu Perumkunnil, Stefan Cosemans, Farrukh Yasin, Sebastien Couet, Robert Carpenter, Barry J. O'Sullivan, Shamin H. Sharifi, N. Jossart, Laurent Souriau, Ludovic Goux, Dimitri Crotti, Gouri Sankar Kar:
STT-MRAM array performance improvement through optimization of Ion Beam Etch and MTJ for Last-Level Cache application. IMW 2021: 1-4 - [c5]Simon Van Beek, Siddharth Rao, Shreya Kundu, Woojin Kim, Barry J. O'Sullivan, Stefan Cosemans, Farrukh Yasin, Robert Carpenter, Sebastien Couet, Shamin H. Sharifi, Nico Jossart, Davide Crotti, Gouri Sankar Kar:
Edge-induced reliability & performance degradation in STT-MRAM: an etch engineering solution. IRPS 2021: 1-5
2010 – 2019
- 2019
- [c4]Trong Huynh Bao, Anabela Veloso, Sushil Sakhare, Philippe Matagne, Julien Ryckaert, Manu Perumkunnil, Davide Crotti, Farrukh Yasin, Alessio Spessot, Arnaud Furnémont, Gouri Sankar Kar, Anda Mocuta:
Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications. DAC 2019: 13 - [c3]Lizhou Wu, Siddharth Rao, Guilherme Cardoso Medeiros, Mottaqiallah Taouil, Erik Jan Marinissen, Farrukh Yasin, Sebastien Couet, Said Hamdioui, Gouri Sankar Kar:
Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing. ETS 2019: 1-6 - [c2]Kevin Garello, Farrukh Yasin, Hubert Hody, S. Couet, Laurent Souriau, Shamin H. Sharifi, Johan Swerts, Robert Carpenter, Sidharth Rao, Wonsub Kim, J. Wu, K. K. V. Sethu, M. Pak, N. Jossart, D. Crotti, Arnaud Furnémont, Gouri Sankar Kar:
Manufacturable 300mm platform solution for Field-Free Switching SOT-MRAM. VLSI Circuits 2019: 194- - 2018
- [c1]Barry J. O'Sullivan, Simon Van Beek, Philippe J. Roussel, Sidharth Rao, Wonsub Kim, S. Couet, Johan Swerts, Farrukh Yasin, Dimitri Crotti, Dimitri Linten, Gouri Sankar Kar:
Extended RVS characterisation of STT-MRAM devices: Enabling detection of AP/P switching and breakdown. IRPS 2018: 5-1 - [i1]Kevin Garello, Farrukh Yasin, S. Couet, Laurent Souriau, Johan Swerts, Sidharth Rao, Simon Van Beek, Wonsub Kim, Enlong Liu, Shreya Kundu, Diana Tsvetanova, N. Jossart, Kris Croes, E. Grimaldi, M. Baumgartner, D. Crotti, Arnaud Furnémont, Pietro Gambardella, Gouri Sankar Kar:
SOT-MRAM 300mm integration for low power and ultrafast embedded memories. CoRR abs/1810.10356 (2018)
Coauthor Index
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