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2010 – 2019
- 2019
[j18]Chih-Wen Lu
, Pei-Yi Lai Lee, You-Gang Chang, Xing-Wei Huang, Jhih-Siou Cheng, Po-Yu Tseng, Chih-Hsien Chou, Poki Chen, Tsin-Yuan Chang, Jenny Yi-Chun Liu:
A 10-bit 1026-Channel Column Driver IC With Partially Segmented Piecewise Linear Digital-to-Analog Converters for UHD TFT-LCDs With One Billion Color Display. IEEE J. Solid State Circuits 54(10): 2703-2716 (2019)- 2014
- [j17]Yuan-Ho Chen, Jyun-Neng Chen, Tsin-Yuan Chang, Chih-Wen Lu:
High-Throughput Multistandard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. 22(3): 463-474 (2014) - [j16]Yuan-Ho Chen, Ruei-Yuan Jou, Tsin-Yuan Chang, Chih-Wen Lu:
A High-Throughput and Area-Efficient Video Transform Core With a Time Division Strategy. IEEE Trans. Very Large Scale Integr. Syst. 22(11): 2268-2277 (2014) - [c19]Hsi-En Liu, Shih-Che Hung, Chih-Wen Lu, Tsin-Yuan Chang:
A low-power Spread Spectrum Clock Generator with an embeddable half-integer division ratio interpolator. ISCAS 2014: 1873-1876 - 2012
- [j15]Song-Nien Tang, Chi-Hsiang Liao, Tsin-Yuan Chang:
An Area- and Energy-Efficient Multimode FFT Processor for WPAN/WLAN/WMAN Systems. IEEE J. Solid State Circuits 47(6): 1419-1435 (2012) - [j14]Yuan-Ho Chen, Tsin-Yuan Chang:
A High-Accuracy Adaptive Conditional-Probability Estimator for Fixed-Width Booth Multipliers. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(3): 594-603 (2012) - [j13]Chung-Yi Li, Yuan-Ho Chen, Tsin-Yuan Chang, Lih-Yuan Deng, Kiwing To:
Period Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG. IEEE Trans. Very Large Scale Integr. Syst. 20(2): 385-389 (2012) - [j12]Yuan-Ho Chen, Tsin-Yuan Chang:
A High Performance Video Transform Engine by Using Space-Time Scheduling Strategy. IEEE Trans. Very Large Scale Integr. Syst. 20(4): 655-664 (2012) - 2011
- [j11]Yuan-Ho Chen, Chung-Yi Li, Tsin-Yuan Chang:
Area-Effective and Power-Efficient Fixed-Width Booth Multipliers Using Generalized Probabilistic Estimation Bias. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(3): 277-288 (2011) - [j10]Chung-Yi Li, Yuan-Ho Chen, Tsin-Yuan Chang, Jyun-Neng Chen:
A Probabilistic Estimation Bias Circuit for Fixed-Width Booth Multiplier and Its DCT Applications. IEEE Trans. Circuits Syst. II Express Briefs 58-II(4): 215-219 (2011) - [j9]Yuan-Ho Chen, Tsin-Yuan Chang, Chung-Yi Li:
High Throughput DA-Based DCT With High Accuracy Error-Compensated Adder Tree. IEEE Trans. Very Large Scale Integr. Syst. 19(4): 709-714 (2011) - 2010
- [j8]Po-Lin Chen, Yu-Chieh Huang, Tsin-Yuan Chang:
Fast Test Integration: Toward Plug-and-Play At-Speed Testing of Multiple Clock Domains Based on IEEE Standard 1500. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1837-1842 (2010) - [j7]Song-Nien Tang, Jui-Wei Tsai, Tsin-Yuan Chang:
A 2.4-GS/s FFT Processor for OFDM-Based WPAN Applications. IEEE Trans. Circuits Syst. II Express Briefs 57-II(6): 451-455 (2010)
2000 – 2009
- 2009
- [j6]Po-Lin Chen, Jhih-Wei Lin, Tsin-Yuan Chang:
IEEE Standard 1500 Compatible Delay Test Framework. IEEE Trans. Very Large Scale Integr. Syst. 17(8): 1152-1156 (2009) - 2008
- [j5]Hung-Chih Lin, Hsiang-Han Wu, Tsin-Yuan Chang:
An Active-Frequency Compensation Scheme for CMOS Low-Dropout Regulators With Transient-Response Improvement. IEEE Trans. Circuits Syst. II Express Briefs 55-II(9): 853-857 (2008) - [c18]Hung-Chih Lin, Bou-Ching Fung, Tsin-Yuan Chang:
A current mode adaptive on-time control scheme for fast transient DC-DC converters. ISCAS 2008: 2602-2605 - [c17]Chung-Yi Li, Chih-Feng Chien, Jin-Hua Hong, Tsin-Yuan Chang:
An Efficient Area-Delay Product Design for MixColumns/InvMixColumns in AES. ISVLSI 2008: 503-506 - 2006
- [c16]Chung-Yi Li, Chia-yuan Chou, Tsin-Yuan Chang:
A Self-Referred Clock Jitter Measurement Circuit in Wide Frequency Range. ATS 2006: 313-317 - [c15]Chung-Yi Li, Jiung-Sheng Chen, Tsin-Yuan Chang:
A chaos-based pseudo random number generator using timing-based reseeding method. ISCAS 2006 - 2005
- [c14]Chih-Feng Li, Shao-Sheng Yang, Tsin-Yuan Chang:
On-chip accumulated jitter measurement for phase-locked loops. ASP-DAC 2005: 1184-1187 - 2004
- [j4]Ming-Jun Hsiao, Jing-Reng Huang, Tsin-Yuan Chang:
A Built-In Parametric Timing Measurement Unit. IEEE Des. Test Comput. 21(4): 322-330 (2004) - [c13]Kae-Jiun Mo, Shao-Sheng Yang, Tsin-Yuan Chang:
Timing measurement unit with multi-stage TVC for embedded memories. ASP-DAC 2004: 565-566 - [c12]Yi-Ming Sheng, Ming-Jun Hsiao, Tsin-Yuan Chang:
A Measurement Unit for Input Signal Analysis of SRAM Sense Amplifier. Asian Test Symposium 2004: 272-276 - 2003
- [c11]Shao-Sheng Yang, Pao-Lin Guo, Tsin-Yuan Chang, Jin-Hua Hong:
A multi-phase charge-sharing technique without external capacitor for low-power TFT-LCD column drivers. ISCAS (5) 2003: 365-368 - 2002
- [c10]Shu-Rong Lee, Ming-Jun Hsiao, Tsin-Yuan Chang:
An Access Timing Measurement Unit of Embedded Memory. Asian Test Symposium 2002: 104- - [c9]Sheng-Hung Hsieh, Ming-Jun Hsiao, Tsin-Yuan Chang:
An Embedded Built-In-Self-Test Approach for Analog-to-Digital Converters. Asian Test Symposium 2002: 266- - 2001
- [c8]Jeng-Horng Tsai, Ming-Jun Hsiao, Tsin-Yuan Chang:
An Embedded Built-in-Self-Test Approach for Digital-to-Analog Converters. Asian Test Symposium 2001: 423- - [c7]Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang:
A low-cost CMOS time interval measurement core. ISCAS (4) 2001: 190-193 - [c6]Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang:
A built-in timing parametric measurement unit. ITC 2001: 315-322 - 2000
- [c5]Yea-Ling Horng, Jing-Reng Huang, Tsin-Yuan Chang:
A realistic fault model for flash memories. Asian Test Symposium 2000: 274-281 - [c4]Tsin-Yuan Chang, Yervant Zorian:
SoC Testing and P1500 Standard. Asian Test Symposium 2000: 492
1990 – 1999
- 1999
- [j3]Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang:
A Programmable BIST Core for Embedded DRAM. IEEE Des. Test Comput. 16(1): 59-70 (1999) - 1992
- [c3]Tsin-Yuan Chang, Jean-Bean Hsu, Cheng-Chi Wang, Yu-Shen Lin:
A design for concurrent error detections in FPLAs. Great Lakes Symposium on VLSI 1992: 9-15 - 1990
- [j2]Chin-Long Wey, Tsin-Yuan Chang:
An efficient output phase assignment for PLA minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(1): 1-7 (1990) - [c2]Chin-Long Wey, Jyhyeung Ding, Tsin-Yuan Chang:
Design of Repairable and Fully Diagnosable Folded PLAs for Yield Enhancement. DAC 1990: 327-332
1980 – 1989
- 1989
- [j1]Tsin-Yuan Chang, Chin-Long Wey:
Design of fault diagnosable and repairable PLA's. IEEE J. Solid State Circuits 24(5): 1451-1454 (1989) - 1988
- [c1]Chin-Long Wey, Tsin-Yuan Chang:
PLAYGROUND: Minimization of PLAs with Mixed Ground True Outputs. DAC 1988: 421-426
Coauthor Index
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