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2020 – today
- 2021
[c9]Hiroaki Kikuchi, Michihiro Yamada, Kazuki Ikegami, Koji Inui:
Best Security Measures to Reduce Cyber-Incident and Data Breach Risks. DPM/CBT@ESORICS 2021: 3-19
2010 – 2019
- 2019
- [c8]Michihiro Yamada, Hiroaki Kikuchi, Naoki Matsuyama, Koji Inui:
Mathematical Model to Estimate Loss by Cyber Incident in Japan. ICISSP 2019: 353-360 - [c7]Kazuki Ikegami, Michihiro Yamada, Hiroaki Kikuchi, Koji Inui:
Development of a Cyber Incident Information Crawler. IMIS 2019: 447-455 - 2018
- [c6]Michihiro Yamada, Riko Shigeno, Hiroaki Kikuchi, Maki Sakamoto:
Evaluation and Development of Onomatopoeia CAPTCHAs. PST 2018: 1-2 - 2017
- [c5]Koichi Niihara, Michihiro Yamada, Hiroaki Kikuchi:
Sharing or Non-sharing Credentials: A Study of What Motivates People to Be Malicious Insiders. HCI (22) 2017: 353-365 - [c4]Michihiro Yamada, Koichi Niihara, Hiroaki Kikuchi:
Decision Tree Analysis on Environmental Factors of Insider Threats. HCI (30) 2017: 658-662 - [c3]Hiroaki Kikuchi, Koichi Niihara, Michihiro Yamada:
How Much is Risk Increased by Sharing Credential in Group? STM 2017: 103-117
2000 – 2009
- 2001
- [j7]Tadaaki Yamauchi, Mitsuya Kinoshita, Teruhiko Amano, Katsumi Dosaka, Kazutami Arimoto, Hideyuki Ozaki, Michihiro Yamada, Tsutomu Yoshihara:
Design methodology of embedded DRAM with virtual-socket architecture. IEEE J. Solid State Circuits 36(1): 46-54 (2001)
1990 – 1999
- 1999
- [j6]Yasunobu Nakase, Yoshikazu Morooka, David J. Perlman, Daniel J. Kolor, Jae-Myoung Choi, Hyun J. Shin, Tsutomu Yoshimura, Naoya Watanabe, Yoshio Matsuda, Masaki Kumanoya, Michihiro Yamada:
Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface. IEEE J. Solid State Circuits 34(4): 494-501 (1999) - [j5]Akira Yamazaki, Tadato Yamagata, Makoto Hatakenaka, Atsushi Miyanishi, Isao Hayashi, Shigeki Tomishima
, Atsuo Mangyo, Yoshio Yukinari, Takashi Tatsumi, Masashi Matsumura, Kazutami Arimoto, Michihiro Yamada:
A 5.3-GB/s embedded SDRAM core with slight-boost scheme. IEEE J. Solid State Circuits 34(5): 661-669 (1999) - 1998
- [j4]Takeshi Hamamoto, Masaki Tsukude, Kazutami Arimoto, Yasuhiro Konishi, Takayuki Miyamoto, Hideyuki Ozaki, Michihiro Yamada:
400-MHz random column operating SDRAM techniques with self-skew compensation. IEEE J. Solid State Circuits 33(5): 770-778 (1998) - [j3]Hirotoshi Sato, Hideaki Nagaoka, Hiroaki Honda, Yukio Maki, Tomohisa Wada, Yutaka Arita, Kazuhito Tsutsumi, Makoto Taniguchi, Michihiro Yamada:
A 5-MHz, 3.6-mW, 1.4-V SRAM with nonboosted, vertical bipolar bit-line contact memory cell. IEEE J. Solid State Circuits 33(11): 1672-1681 (1998) - 1997
- [j2]Takahiro Tsuruda, Mako Kobayashi, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto, Michihiro Yamada:
High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI's. IEEE J. Solid State Circuits 32(3): 477-482 (1997) - 1991
- [c2]Yoshikazu Morooka, Shigeru Mori, Hiroshi Miyamoto, Michihiro Yamada:
An Address Maskable Parallel Testing for Ultra High Density DRAMs. ITC 1991: 556-563
1980 – 1989
- 1989
- [j1]Kazutami Arimoto, Kazuyasu Fujishima, Yoshio Matsuda, Masaki Tsukude, Tukasa Oishi, Wataru Wakamiya, Shin'ichi Satoh, Michihiro Yamada, Takao Nakano:
A 60-ns 3.3-V-only 16-Mbit DRAM with multipurpose register. IEEE J. Solid State Circuits 24(5): 1184-1190 (1989) - 1985
- [c1]Hiroshi Miyamoto, Koichiro Mashiko, Yoshikazu Morooka, Kazutami Arimoto, Michihiro Yamada, Takao Nakano:
Test Pattern Considerations for Fault Tolerant High Density DRAM. ITC 1985: 451-455
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