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2020 – today
- 2024
[j3]Sunan Zou
, Jiaxi Zhang, Bizhao Shi, Guojie Luo:
PowerSyn: A Logic Synthesis Framework With Early Power Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(1): 203-216 (2024)- [j2]Tuo Dai, Bizhao Shi, Guojie Luo:
Weave: Abstraction and Integration Flow for Accelerators of Generated Modules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(3): 854-867 (2024) - [c12]Tuo Dai, Bizhao Shi, Guojie Luo:
G2PM: Performance Modeling for ACAP Architecture with Dual-Tiered Graph Representation Learning. DAC 2024: 13:1-13:6 - [c11]Bizhao Shi, Tuo Dai, Jiaxi Zhang, Xuechao Wei, Guojie Luo:
PT-Map: Efficient Program Transformation Optimization for CGRA Mapping. DAC 2024: 14:1-14:6 - [c10]Tuo Dai, Bizhao Shi, Guojie Luo:
WideSA: A High Array Utilization Mapping Scheme for Uniform Recurrences on ACAP. DATE 2024: 1-6 - [c9]Sunan Zou, Jiaxi Zhang, Bizhao Shi, Guojie Luo:
BESWAC: Boosting Exact Synthesis via Wiser SAT Solver Call. DATE 2024: 1-6 - [c8]Bizhao Shi, Tuo Dai, Sunan Zou, Xinming Wei, Guojie Luo:
ImageMap: Enabling Efficient Mapping from Image Processing DSL to CGRA. Euro-Par (1) 2024: 61-76 - [i2]Tuo Dai, Bizhao Shi, Guojie Luo:
WideSA: A High Array Utilization Mapping Scheme for Uniform Recurrences on the Versal ACAP Architecture. CoRR abs/2401.16792 (2024) - 2023
- [j1]Bizhao Shi, Jiaxi Zhang, Zhuolun He, Xuechao Wei, Sicheng Li, Guojie Luo, Hongzhong Zheng, Yuan Xie:
Efficient Super-Resolution System With Block-Wise Hybridization and Quantized Winograd on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 3910-3924 (2023) - [c7]Tuo Dai, Bizhao Shi, Guojie Luo:
Weave: Abstraction for Accelerator Integration of Generated Modules. FPGA 2023: 51 - [c6]Bizhao Shi, Jieran Zhang, Guojie Luo:
F-TFM: Accelerating Total Focusing Method for Ultrasonic Array Imaging on FPGA. ICFPT 2023: 280-281 - [c5]Xiong Wang, Jun Huang, Bizhao Shi, Zhe Ou, Guojie Luo, Linghe Kong, Daqing Zhang, Chenren Xu:
RF-SIFTER: Sifting Signals at Layer-0.5 to Mitigate Wideband Cross-Technology Interference for IoT. MobiCom 2023: 12:1-12:14 - 2022
- [c4]Jiaxi Zhang, Qiuyang Gao, Yijiang Guo, Bizhao Shi, Guojie Luo:
EasyMAC: Design Exploration-Enabled Multiplier-Accumulator Generator Using a Canonical Architectural Representation: (Invited Paper). ASP-DAC 2022: 647-653 - [c3]Sicheng Li, Chen Bai, Xuechao Wei, Bizhao Shi, Yen-Kuang Chen, Yuan Xie:
2022 ICCAD CAD Contest Problem C: Microarchitecture Design Space Exploration. ICCAD 2022: 95:1-95:7 - 2021
- [c2]Zhe Zhou, Bizhao Shi, Zhe Zhang, Yijin Guan, Guangyu Sun, Guojie Luo:
BlockGNN: Towards Efficient GNN Acceleration Using Block-Circulant Weight Matrices. DAC 2021: 1009-1014 - [i1]Zhe Zhou, Bizhao Shi, Zhe Zhang, Yijin Guan, Guangyu Sun, Guojie Luo:
BlockGNN: Towards Efficient GNN Acceleration Using Block-Circulant Weight Matrices. CoRR abs/2104.06214 (2021)
2010 – 2019
- 2019
- [c1]Bizhao Shi, Zhucheng Tang, Guojie Luo, Ming Jiang:
Winograd-Based Real-Time Super-Resolution System on FPGA. FPT 2019: 423-426
Coauthor Index
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