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Xuechao Wei
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2020 – today
- 2024
- [c19]Bizhao Shi, Tuo Dai, Jiaxi Zhang, Xuechao Wei, Guojie Luo:
PT-Map: Efficient Program Transformation Optimization for CGRA Mapping. DAC 2024: 14:1-14:6 - [c18]Yifei Li, Bole Zhou, Jiejing Zhang, Xuechao Wei, Yinghan Li, Yingda Chen:
RadiK: Scalable and Optimized GPU-Parallel Radix Top-K Selection. ICS 2024: 537-548 - [c17]Yifei Li, Bole Zhou, Jiejing Zhang, Xuechao Wei, Yinghan Li, Yingda Chen:
POSTER: RadiK: Scalable Radix Top-K Selection on GPUs. PPoPP 2024: 472-474 - 2023
- [j3]Bizhao Shi, Jiaxi Zhang, Zhuolun He, Xuechao Wei, Sicheng Li, Guojie Luo, Hongzhong Zheng, Yuan Xie:
Efficient Super-Resolution System With Block-Wise Hybridization and Quantized Winograd on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 3910-3924 (2023) - [j2]Zhengzheng Ma, Tuo Dai, Xuechao Wei, Guojie Luo:
An Intermediate-Centric Dataflow for Transposed Convolution Acceleration on FPGA. ACM Trans. Embed. Comput. Syst. 22(6): 92:1-92:22 (2023) - [c16]Chen Bai, Xuechao Wei, Youwei Zhuo, Yi Cai, Hongzhong Zheng, Bei Yu, Yuan Xie:
Klotski: DNN Model Orchestration Framework for Dataflow Architecture Accelerators. ICCAD 2023: 1-9 - [c15]Chen Bai, Jiayi Huang, Xuechao Wei, Yuzhe Ma, Sicheng Li, Hongzhong Zheng, Bei Yu, Yuan Xie:
ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis. MICRO 2023: 268-282 - 2022
- [c14]Zhe Zhou, Cong Li, Xuechao Wei, Xiaoyang Wang, Guangyu Sun:
GNNear: Accelerating Full-Batch Training of Graph Neural Networks with near-Memory Processing. PACT 2022: 54-68 - [c13]Sicheng Li, Chen Bai, Xuechao Wei, Bizhao Shi, Yen-Kuang Chen, Yuan Xie:
2022 ICCAD CAD Contest Problem C: Microarchitecture Design Space Exploration. ICCAD 2022: 95:1-95:7 - [c12]Zhe Zhou, Xuechao Wei, Jiejing Zhang, Guangyu Sun:
PetS: A Unified Framework for Parameter-Efficient Transformers Serving. USENIX ATC 2022: 489-504 - 2021
- [i1]Zhe Zhou, Cong Li, Xuechao Wei, Guangyu Sun:
GCNear: A Hybrid Architecture for Efficient GCN Training with Near-Memory Processing. CoRR abs/2111.00680 (2021) - 2020
- [j1]Liancheng Jia, Liqiang Lu, Xuechao Wei, Yun Liang:
Generating Systolic Array Accelerators With Reusable Blocks. IEEE Micro 40(4): 85-92 (2020) - [c11]Runbin Shi, Yuhao Ding, Xuechao Wei, He Li, Hang Liu, Hayden Kwok-Hay So, Caiwen Ding:
FTDL: A Tailored FPGA-Overlay for Deep Learning with High Scalability. DAC 2020: 1-6 - [c10]Runbin Shi, Yuhao Ding, Xuechao Wei, Hang Liu, Hayden Kwok-Hay So, Caiwen Ding:
FTDL: An FPGA-tailored Architecture for Deep Learning Systems. FPGA 2020: 320
2010 – 2019
- 2019
- [c9]Xuechao Wei, Yun Liang, Jason Cong:
Overcoming Data Transfer Bottlenecks in FPGA-based DNN Accelerators via Layer Conscious Memory Management. DAC 2019: 125 - [c8]Xuechao Wei, Yun Liang, Peng Zhang, Cody Hao Yu, Jason Cong:
Overcoming Data Transfer Bottlenecks in DNN Accelerators via Layer-Conscious Memory Managment. FPGA 2019: 120 - [c7]Jiaxi Zhang, Wentai Zhang, Guojie Luo, Xuechao Wei, Yun Liang, Jason Cong:
Frequency Improvement of Systolic Array-Based CNNs on FPGAs. ISCAS 2019: 1-4 - 2018
- [c6]Xuechao Wei, Yun Liang, Xiuhong Li, Cody Hao Yu, Peng Zhang, Jason Cong:
TGPA: tile-grained pipeline architecture for low latency CNN inference. ICCAD 2018: 58 - 2017
- [c5]Xuechao Wei, Yun Liang, Tao Wang, Songwu Lu, Jason Cong:
Throughput optimization for streaming applications on CPU-FPGA heterogeneous systems. ASP-DAC 2017: 488-493 - [c4]Xuechao Wei, Cody Hao Yu, Peng Zhang, Youxiang Chen, Yuxin Wang, Han Hu, Yun Liang, Jason Cong:
Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs. DAC 2017: 29:1-29:6 - 2012
- [c3]Mengjie Mao, Hong An, Tao Sun, Qi Li, Bobin Deng, Xuechao Wei, Junrui Zhou:
Distributed Control Independence for Composable Multi-processors. ACIS-ICIS 2012: 124-129 - [c2]Mengjie Mao, Hong An, Bobin Deng, Tao Sun, Xuechao Wei, Wei Zhou, Wenting Han:
Distributed replay protocol for distributed uniprocessors. ICS 2012: 3-14 - [c1]Gu Liu, Hong An, Wenting Han, Xiaoqiang Li, Tao Sun, Wei Zhou, Xuechao Wei, Xulong Tang:
FlexBFS: a parallelism-aware implementation of breadth-first search on GPU. PPoPP 2012: 279-280
Coauthor Index
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last updated on 2024-11-13 23:53 CET by the dblp team
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