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ORCIDMarcelo Orenes-Vera
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2020 – today
- 2024
[b1]Marcelo Orenes-Vera:
Navigating Heterogeneity and Scalability in Modern Chip Design. Princeton University, USA, 2024- [c11]Marcelo Orenes-Vera, Esin Tureci, Margaret Martonosi, David Wentzlaff:
MuchiSim: A Simulation Framework for Design Exploration of Multi-Chip Manycore Systems. ISPASS 2024: 48-60 - 2023
- [c10]Tianrui Wei
, Nazerke Turtayeva, Marcelo Orenes-Vera, Omkar Lonkar, Jonathan Balkind:
Cohort: Software-Oriented Acceleration for Heterogeneous SoCs. ASPLOS (3) 2023: 105-117 - [c9]Ting-Jung Chang, Ang Li, Fei Gao, Tuan Ta, Georgios Tziantzioulis, Yanghui Ou, Moyang Wang, Jinzheng Tu, Kaifeng Xu, Paul J. Jackson, August Ning, Grigory Chirkov, Marcelo Orenes-Vera, Shady Agwa, Xiaoyu Yan, Eric Tang, Jonathan Balkind, Christopher Batten, David Wentzlaff:
CIFER: A 12nm, 16mm2, 22-Core SoC with a 1541 LUT6/mm2 1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA. CICC 2023: 1-2 - [c8]Fei Gao, Ting-Jung Chang, Ang Li, Marcelo Orenes-Vera, Davide Giri, Paul J. Jackson, August Ning, Georgios Tziantzioulis, Joseph Zuckerman, Jinzheng Tu, Kaifeng Xu, Grigory Chirkov, Gabriele Tombesi, Jonathan Balkind, Margaret Martonosi, Luca P. Carloni, David Wentzlaff:
DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET. CICC 2023: 1-2 - [c7]Marcelo Orenes-Vera, Esin Tureci, David Wentzlaff, Margaret Martonosi:
Dalorex: A Data-Local Program Execution and Architecture for Memory-bound Applications. HPCA 2023: 718-730 - [c6]Marcelo Orenes-Vera, Ilya Sharapov, Robert Schreiber, Mathias Jacquelin, Philippe Vandermersch, Sharan Chetlur:
Wafer-Scale Fast Fourier Transforms. ICS 2023: 180-191 - [c5]Marcelo Orenes-Vera, Hyunsung Yun, Nils Wistoff, Gernot Heiser, Luca Benini, David Wentzlaff, Margaret Martonosi:
AutoCC: Automatic Discovery of Covert Channels in Time-Shared Hardware. MICRO 2023: 871-885 - [i9]Marcelo Orenes-Vera, Esin Tureci, David Wentzlaff, Margaret Martonosi:
Massive Data-Centric Parallelism in the Chiplet Era. CoRR abs/2304.09389 (2023) - [i8]Marcelo Orenes-Vera, Margaret Martonosi, David Wentzlaff:
Using LLMs to Facilitate Formal Verification of RTL. CoRR abs/2309.09437 (2023) - [i7]Marcelo Orenes-Vera, Esin Tureci, Margaret Martonosi, David Wentzlaff:
DCRA: A Distributed Chiplet-based Reconfigurable Architecture for Irregular Applications. CoRR abs/2311.15443 (2023) - [i6]Marcelo Orenes-Vera, Esin Tureci, David Wentzlaff, Margaret Martonosi:
Tascade: Hardware Support for Atomic-free, Asynchronous and Efficient Reduction Trees. CoRR abs/2311.15810 (2023) - [i5]Marcelo Orenes-Vera, Esin Tureci, Margaret Martonosi, David Wentzlaff:
Muchisim: A Simulation Framework for Design Exploration of Multi-Chip Manycore Systems. CoRR abs/2312.10244 (2023) - 2022
- [c4]Marcelo Orenes-Vera, Aninda Manocha, Jonathan Balkind, Fei Gao, Juan L. Aragón, David Wentzlaff, Margaret Martonosi:
Tiny but mighty: designing and realizing scalable latency tolerance for manycore SoCs. ISCA 2022: 817-830 - [i4]Marcelo Orenes-Vera, Esin Tureci, David Wentzlaff, Margaret Martonosi:
Dalorex: A Data-Local Program Execution and Architecture for Memory-bound Applications. CoRR abs/2207.13219 (2022) - [i3]Marcelo Orenes-Vera, Ilya Sharapov, Robert Schreiber, Mathias Jacquelin, Philippe Vandermersch, Sharan Chetlur:
Wafer-Scale Fast Fourier Transforms. CoRR abs/2209.15040 (2022) - 2021
- [j1]Marcelo Orenes-Vera, Fernando Terroso-Saenz, Mercedes Valdés-Vela:
RECITE: A framework for user trajectory analysis in cultural sites. J. Ambient Intell. Smart Environ. 13(5): 389-409 (2021) - [c3]Marcelo Orenes-Vera, Aninda Manocha, David Wentzlaff, Margaret Martonosi:
AutoSVA: Democratizing Formal Verification of RTL Module Interactions. DAC 2021: 535-540 - [i2]Marcelo Orenes-Vera, Aninda Manocha, David Wentzlaff, Margaret Martonosi:
AutoSVA: Democratizing Formal Verification of RTL Module Interactions. CoRR abs/2104.04003 (2021) - 2020
- [c2]Tyler Sorensen, Aninda Manocha, Esin Tureci, Marcelo Orenes-Vera, Juan L. Aragón, Margaret Martonosi:
A Simulator and Compiler Framework for Agile Hardware-Software Co-design Evaluation and Exploration. ICCAD 2020: 97:1-97:9 - [c1]Opeoluwa Matthews, Aninda Manocha, Davide Giri, Marcelo Orenes-Vera, Esin Tureci, Tyler Sorensen, Tae Jun Ham, Juan L. Aragón, Luca P. Carloni, Margaret Martonosi:
MosaicSim: A Lightweight, Modular Simulator for Heterogeneous Systems. ISPASS 2020: 136-148 - [i1]Opeoluwa Matthews, Aninda Manocha, Davide Giri, Marcelo Orenes-Vera, Esin Tureci, Tyler Sorensen, Tae Jun Ham, Juan L. Aragón, Luca P. Carloni, Margaret Martonosi:
The MosaicSim Simulator (Full Technical Report). CoRR abs/2004.07415 (2020)
Coauthor Index
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