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ORCIDSamuel Spetalnick
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2020 – today
- 2024
[j3]Ashwin Sanjay Lele
, Muya Chang, Samuel D. Spetalnick, Brian Crafton, Shota Konno, Zishen Wan, Ashwin Bhat, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking. IEEE J. Solid State Circuits 59(1): 52-64 (2024)- [c18]Zishen Wan, Che-Kai Liu, Mohamed Ibrahim, Hanchen Yang, Samuel Spetalnick, Tushar Krishna, Arijit Raychowdhury:
H3DFact: Heterogeneous 3D Integrated CIM for Factorization with Holographic Perceptual Representations. DATE 2024: 1-6 - [c17]Samuel D. Spetalnick, Ashwin Sanjay Lele, Brian Crafton, Muya Chang, Sigang Ryu, Jong-Hyeok Yoon, Zhijian Hao, Azadeh Ansari, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance. ISSCC 2024: 482-484 - [c16]Brian Crafton, Samuel D. Spetalnick, Muya Chang, Arijit Raychowdhury:
A 28nm Approximate / Binary 6T CAM for Sequence Alignment. VLSI Technology and Circuits 2024: 1-2 - [i3]Zishen Wan, Che-Kai Liu, Mohamed Ibrahim, Hanchen Yang, Samuel Spetalnick, Tushar Krishna, Arijit Raychowdhury:
H3DFact: Heterogeneous 3D Integrated CIM for Factorization with Holographic Perceptual Representations. CoRR abs/2404.04173 (2024) - 2023
- [c15]Ashwin Sanjay Lele, Muya Chang, Samuel D. Spetalnick, Brian Crafton, Arijit Raychowdhury, Yan Fang:
Neuromorphic Swarm on RRAM Compute-in-Memory Processor for Solving QUBO Problem. DAC 2023: 1-6 - [c14]Ashwin Sanjay Lele, Muya Chang, Samuel Spetalnick, Yan Fang, Brian Crafton, Shota Konno, Arijit Raychowdhury:
Live Demonstration: Hybrid RRAM and SRAM SoC for Fused Frame and Event Target Tracking. ISCAS 2023: 1 - [c13]Muya Chang, Ashwin Sanjay Lele, Samuel D. Spetalnick, Brian Crafton, Shota Konno, Zishen Wan, Ashwin Bhat, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking. ISSCC 2023: 426-427 - [c12]Samuel D. Spetalnick, Muya Chang, Shota Konno, Brian Crafton, Ashwin Sanjay Lele, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
A 2.38 MCells/mm2 9.81 -350 TOPS/W RRAM Compute-in-Memory Macro in 40nm CMOS with Hybrid Offset/IOFF Cancellation and ICELL RBLSL Drop Mitigation. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j2]Samuel Spetalnick, Arijit Raychowdhury:
A Practical Design-Space Analysis of Compute-in-Memory With SRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 69(4): 1466-1479 (2022) - [c11]Brian Crafton, Zishen Wan, Samuel Spetalnick, Jong-Hyeok Yoon, Wei Wu, Carlos Tokunaga, Vivek De, Arijit Raychowdhury:
Improving compute in-memory ECC reliability with successive correction. DAC 2022: 745-750 - [c10]Brian Crafton, Connor Talley, Samuel Spetalnick, Jong-Hyeok Yoon, Arijit Raychowdhury:
Characterization and Mitigation of IR-Drop in RRAM-based Compute In-Memory. ISCAS 2022: 70-74 - [c9]Muya Chang, Samuel D. Spetalnick, Brian Crafton, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
A 40nm 60.64TOPS/W ECC-Capable Compute-in-Memory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems. ISSCC 2022: 1-3 - [c8]Samuel D. Spetalnick, Muya Chang, Brian Crafton, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
A 40nm 64kb 26.56TOPS/W 2.37Mb/mm2RRAM Binary/Compute-in-Memory Macro with 4.23x Improvement in Density and >75% Use of Sensing Dynamic Range. ISSCC 2022: 1-3 - [c7]Wriddhi Chakraborty, P. Shrestha, A. Gupta, Rakshith Saligram, Samuel Spetalnick, J. Campbell, Arijit Raychowdhury, Suman Datta:
Multi-bit per-cell 1T SiGe Floating Body RAM for Cache Memory in Cryogenic Computing. VLSI Technology and Circuits 2022: 302-303 - 2021
- [j1]Brian Crafton, Samuel Spetalnick, Yan Fang, Arijit Raychowdhury:
Merged Logic and Memory Fabrics for Accelerating Machine Learning Workloads. IEEE Des. Test 38(1): 39-68 (2021) - [c6]Brian Crafton, Samuel Spetalnick, Arijit Raychowdhury:
Merged Logic and Memory Fabrics for AI Workloads. ASP-DAC 2021: 305-310 - [c5]Brian Crafton, Samuel Spetalnick, Jong-Hyeok Yoon, Wei Wu, Carlos Tokunaga, Vivek De, Arijit Raychowdhury:
CIM-SECDED: A 40nm 64Kb Compute In-Memory RRAM Macro with ECC Enabling Reliable Operation. A-SSCC 2021: 1-3 - [c4]Brian Crafton, Samuel Spetalnick, Jong-Hyeok Yoon, Arijit Raychowdhury:
Statistical Optimization of Compute In-Memory Performance Under Device Variation. ISLPED 2021: 1-6 - 2020
- [c3]Jie Zhang, Adam Khalifa, Samuel Spetalnick, Milad Alemohammad, John M. Rattray, Chetan Singh Thakur, Adebayo Eisape, Ralph Etienne-Cummings:
A Miniature Wireless Silicon-on-Insulator Image Sensor for Brain Fluorescence Imaging. EMBC 2020: 3403-3406 - [c2]Brian Crafton, Samuel Spetalnick, Gauthaman Murali, Tushar Krishna, Sung Kyu Lim, Arijit Raychowdhury:
Breaking Barriers: Maximizing Array Utilization for Compute in-Memory Fabrics. VLSI-SOC 2020: 123-128 - [c1]Brian Crafton, Samuel Spetalnick, Gauthaman Murali, Tushar Krishna, Sung Kyu Lim, Arijit Raychowdhury:
Statistical Array Allocation and Partitioning for Compute In-Memory Fabrics. VLSI-SoC (Selected Papers) 2020: 323-341 - [i2]Brian Crafton, Samuel Spetalnick, Arijit Raychowdhury:
Counting Cards: Exploiting Weight and Variance Distributions for Robust Compute In-Memory. CoRR abs/2006.03117 (2020) - [i1]Brian Crafton, Samuel Spetalnick, Gauthaman Murali, Tushar Krishna, Sung Kyu Lim, Arijit Raychowdhury:
Breaking Barriers: Maximizing Array Utilization for Compute In-Memory Fabrics. CoRR abs/2008.06741 (2020)
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