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ORCIDA-SSCC 2021: Busan, Korea
- IEEE Asian Solid-State Circuits Conference, A-SSCC 2021, Busan, Korea, Republic of, November 7-10, 2021. IEEE 2021, ISBN 978-1-6654-4350-0
- Jae-Woo Park, Dongsuk Kang, Injae Park, Minsu Park, Xuefan Jin, Kyu-Dong Hwang, Dae-Han Kwon, Jung-Hoon Chun:
A 21Gb/s Duobinary Transceiver for GDDR interfaces with an Adaptive Equalizer. 1-3 - Byeonghun Yun, Dae-Woong Park, Kyung-Sik Choi, Ho-Jin Song, Sang-Gug Lee:
245/243GHz, 9.2/10.5dBm Saturated Output Power, 4.6/2.8% PAE, and 28/26dB Gain Power Amplifiers in 65nm CMOS Adopting 2-and 4-way Power Combining. 1-3 - Feifan Hong
, Tianao Ding, Dixian Zhao:
A 196.2 dBc/Hz FOMT 16.8-to-21.6 GHz Class-F23 VCO with Transformer-Based Optimal Q-factor Tank in 65-nm CMOS. 1-3 - Xiping Jiang, Fengguo Zuo, Song Wang, Xiaofeng Zhou, Bing Yu, Yubing Wang, Qi Liu, Ming Liu, Yi Kang, Qiwei Ren:
A 1596GB/s 48Gb Embedded DRAM 384-Core SoC with Hybrid Bonding Integration. 1-3 - Yen-Kuei Lu, Miao-Shan Li, Ching-Yuan Yang, Chin-Lung Lin:
A 2.7-Gb/s Multiplexed-DLL-Based CDR Circuit for ±10% Clock-Embedded Spread-Spectrum Modulation Depth. 1-3 - Mario Mercandelli, Luca Bertulessi, Carlo Samori, Salvatore Levantino:
A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter. 1-3 - Chaoming Fang, Habib Derbyshire, Wenyu Sun, Jinshan Yue, Haobing Shi, Yongpan Liu:
A Sort-Less FPGA-Based Non-Maximum Suppression Accelerator using Multi-Thread Computing and Binary Max Engine for Object Detection. 1-3 - Wataru Saito, Yoichi Iizuka, Norihito Kato, Ryota Otake, Fukashi Morishita:
A Low Noise and Linearity Improvement CMOS Image Sensor for Surveillance Camera with Skew-Relaxation Local Multiply Circuit and On-Chip Testable Ramp Generator. 1-3 - Ye-Dam Kim, Jae-Hyun Chung, Kent Edrian Lozada, Dong-Jin Chang, Seung-Tak Ryu:
A 4th-order CT I-DSM with Digital Noise Coupling and Input Pre-conversion Method for Initialization. 1-3 - Nandish Mehta, Stephen G. Tell, Walker J. Turner, Lamar Tatro, Giant Goh, C. Thomas Gray:
A 77 MHz Relaxation Oscillator in 5nm FinFET with 3ns TIE over 10K cycles and ±0.3% Thermal Stability using Frequency-Error Feedback Loop. 1-3 - Changhyeon Kim, Dongyoung Rim, Jeongwon Choe, Dongyun Kam, Giyoon Park, Seokki Kim, Youngjoo Lee:
FPGA-Based Ordered Statistic Decoding Architecture for B5G/6G URLLC IIOT Networks. 1-3 - Anand Savanth, Philex Ming-Yan Fan, Sahan Gamage, Thanushree Achuthan, Fernando García-Redondo:
-17 dBm Differential charge pump EPC Gen2 UHF RFID demodulator for 9 dB receive sensitivity boost. 1-3 - Jee-Ho Park, Jung-Hye Hwang, Changyong Shin, Seong-Jin Kim:
A 3.1-μW BJT-Based CMOS Temperature-to-Frequency Converter with Untrimmed Inaccuracy of ±1°C (3σ) from -40°C to 140°C. 1-3 - Dongin Kim, SeongHwan Cho:
An Adaptive Clocking System using Supply Tracking Clock Modulator with Background Calibrated Supply-Sensitivity in 28nm CMOS. 1-3 - Pei-Yi Lai Lee, Ya-Wen Yang, Sih-Han Li, Jian-Jhih Sun, Tzu Yi Hung, Chih-Wen Lu, Yen-Hsiang Fang, Wei-Hung Kuo, Li-Chun Huang, Guo-Dung John Su, Poki Chen:
A 1280 x 720 Micro-LED Display Driver with 10-Bit Current-Mode Pulse Width Modulation. 1-3 - Tongsung Kim, Anil Kavala, Hyunsuk Kang, Youngmin Jo, Jungjune Park, Kyoungtae Kang, Byung-Kwan Chun, Dong-Ho Shin, Dong-Su Jang, Byunghoon Jeong, Chiweon Yoon, Jinyub Lee, Jai Hyuk Song:
A Hybrid ZQ Calibration Design for High-Density Flash Memory Toggle 5.0 High-speed Interface. 1-2 - Wen-Liang Zeng, Caolei Pan, Chi-Seng Lam, Sai-Weng Sin, Chenchang Zhan, Rui Paulo Martins:
A 95% Peak Efficiency Modified KY (Boost) Converter for IoT with Continuous Flying Capacitor Charging in DCM. 1-3 - Shogo Harada, Mahfuzul Islam, Takashi Hisakado, Osami Wada:
A process scalable voltage-reference-free temperature sensor utilizing MOSFET threshold voltage variation. 1-3 - Chongyao Xu, Jieyun Zhang, Man-Kay Law, Yang Jiang, Xiaojin Zhao, Pui-In Mak, Rui Paulo Martins:
Modeling Attack Resistant Strong PUF Exploiting Obfuscated Interconnections With <0.83% Bit-Error Rate. 1-3 - Seung-Yong Lim, Raymond Mabilangan, Dong-Jin Chang, Young-Jae Cho, Michael Choi, Seung-Tak Ryu:
An Input-buffer Embedding Dual-residue Pipelined-SAR ADC with Nonbinary Capacitive Interpolation. 1-3 - Yanchao Wang, Siladitya Dey, Tao He, Lukang Shi, Jiawei Zheng, Manjunath Kareppagoudr, Yi Zhang, Kazuki Sobue, Koichi Hamashita, Koji Tomioka, Gabor C. Temes:
A Hybrid Continuous Time Incremental and SAR Two-Step ADC with 90.5dB DR over 1MHz BW. 1-3 - Yi-Cheng Lin, Ping-Hsuan Hsieh, Jian-Lun Hong, Yu-Hsiang Lai, Jun-Da Chen, Fan-Yi Lin, Yuan-Hao Huang, Po-Chiun Huang:
A Cross-Correlation-Based Time-of-Flight Design for Chaos Lidar Systems. 1-3 - Sumon Kumar Bose, Arindam Basu:
A 389TOPS/W, 1262fps at 1Meps Region Proposal Integrated Circuit for Neuromorphic Vision Sensors in 65nm CMOS. 1-3 - Jue Wang, Zhenyu Yang, Jiawei Wang, Xu Cheng, Jun Han, Xiaoyang Zeng:
A Synthesizable 0.0060mm2 VCO-Based Delta Sigma Modulator with Digital Tri-level Feedback Scheme. 1-3 - Haram Ju, Kwangho Lee, Woosong Jung, Deog-Kyoon Jeong:
A 48Gb/s 2.4pJ/b PAM-4 Baud-Rate Digital CDR with Stochastic Phase Detection Technique in 40nm CMOS. 1-3 - Po-Shao Chen, Yen-Lung Chen, Yu-Chi Lee, Zih-Sing Fu, Chia-Hsiang Yang:
A 28.8mW Accelerator IC for Dark Channel Prior Based Blind Image Deblurring. 1-3 - Dawei Ye, Yuting Tu, Wenjun Gong, Rongjin Xu, Chuanjin Richard Shi:
A Two-Tone Wake-Up Receiver with an Envelope-Detector-First Architecture Using Envelope Biasing and Active Inductor Load Achieving 41/33dB In-Band Rejection to CW/AM Interference. 1-3 - Xi Meng, Junqi Guo, Haoran Li, Jun Yin, Pui-In Mak, Rui Paulo Martins:
A 15.2-to-18.2GHz Balanced Dual-Core Inverse-Class-F VCO with Q-Enhanced 2nd-Harmonic Resonance Achieving 187-to-188.1dBc/Hz FoM in 28nm CMOS. 1-3 - Brian Crafton, Samuel Spetalnick, Jong-Hyeok Yoon, Wei Wu, Carlos Tokunaga, Vivek De, Arijit Raychowdhury:
CIM-SECDED: A 40nm 64Kb Compute In-Memory RRAM Macro with ECC Enabling Reliable Operation. 1-3 - Yan Zeng, Shiheng Yang, Yueduo Liu, Zehao Li, Wengang Huang, Xiaozong Huang, Xiong Zhou, Jiaxin Liu, Qiang Li:
A 640×512 30μm Pixel Pitch 1.8mK-NETD 90.1dB-SNR Digital Read-out Integrated Circuit with Fully On-chip Image Algorithm Pixel-Level Calibration. 1-3 - Surin Gweon, Sanghoon Kang, Donghyeon Han, Kyoung-Rog Lee, Kwantae Kim, Hoi-Jun Yoo:
FlashMAC: An Energy-Efficient Analog-Digital Hybrid MAC with Variable Latency-Aware Scheduling. 1-3 - Jiahao Song, Yuan Wang, Xiyuan Tang, Runsheng Wang, Ru Huang:
A 16Kb Transpose 6T SRAM In-Memory-Computing Macro based on Robust Charge-Domain Computing. 1-3 - Hyeonsik Kim, Seonkyung Kim, Jintae Kim:
1.55mW 2GHz ERBW 7b 800MS/s 3-stage Pipelined SAR ADC in 28nm CMOS using a Kickback-Cancelling 7T-Dynamic Residue Amplifier with only 16fF Input Capacitance. 1-3 - Jinyu Bai, Yunqian Fan, Sifan Sun, Wang Kang, Weisheng Zhao:
Tiny neural network search and implementation for embedded FPGA: a software-hardware co-design approach. 1-3 - Hyungmin Jin, Jindo Byun, Hyunyoon Cho, Hojun Yoon, Jin-Hee Park, Kyoungsoo Kim, Youngdon Choi, Jung-Hwan Choi, Hyungjong Ko, Sang-Hyun Lee:
A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATE. 1-3 - Yu-Ping Huang, Yi-Wei Chang, Wei-Zen Chen:
A 1.68-23.2 Gb/s Reference-Less Half-Rate Receiver with an ISI-Tolerant Unlimited Range Frequency Detector. 1-2 - Yongkuo Ma, Peiyuan Wan, Hongda Zhang, Zhi Wan, Xiaoyu Zhang, Xu Liu, Zhijie Chen:
A 4.39ps, 1.5GS/s Time-to-Digital Converter with 4× Phase Interpolation Technique and a 2-D Quantization Array. 1-3 - Lu Lu, Tony Tae-Hyoung Kim:
A Programmable 6T SRAM-Based PUF with Dynamic Stability Data Masking. 1-3 - Seokhyeon Jeong, Yejoong Kim, Yuyang Li, Inhee Lee:
A Millimeter-Scale Computing System with Adaptive Dynamic Load Power Tracking. 1-3 - Han Xu, Zheyu Liu, Ziwei Li, Erxiang Ren, Maimaiti Nazhamati, Fei Qiao, Li Luo, Qi Wei, Xinjun Liu, Huazhong Yang:
A 4.57 μW@120fps Vision System of Sensing with Computing for BNN-Based Perception Applications. 1-3 - Xin Cheng, Haowen Zhu, Xinyi Xing, Yunfeng Zhang, Yongqiang Zhang, Guangjun Xie, Zhang Zhang:
A Feedback Architecture of High Speed True Random Number Generator based on Ring Oscillator. 1-3 - Byeongseol Kim, Beomjin Yuk, Joonsung Bae:
A Wirelessly-Powered 10Mbps 46-pJ/b Body Channel Communication System with 45% PCE Multi-Stage and Multi-Source Rectifier for Neural Interface Applications. 1-3 - Dong-Hyun Yoon, Dong-Kyu Jung, Kiho Seong, Tae-Hyeok Eom, Jae-Soub Han, Ju Eon Kim, Tony Tae-Hyoung Kim, Kwang-Hyun Baek:
A 3.2 GHz 178fsrms Jitter Injection Locked Clock Multiplier Using Sub-Sampling FTL and DLL for In-Band Noise Improvement. 1-3 - Zain Taufique, Bingzhao Zhu, Gianluca Coppola, Mahsa Shoaran, Wala Saadeh, Muhammad Awais Bin Altaf:
An 8.7 μJ/class. FFT accelerator and DNN-based configurable SoC for Multi-Class Chronic Neurological Disorder Detection. 1-3 - Han Wu, Miaolin Zhang, Jiaqi Guo, Zhichun Shao, Kian Ann Ng, Jiamin Li, Lian Zhang, Yilong Dong, Liuhao Wu, Chne-Wuen Tsai, Ho Yin Benjamin Lee, Liwei Lin, Jerald Yoo:
A 7m-range, 4.3mW/Ch. Ultrasound ASIC with Universal Energy Recycling TX for All-Weather Metamorphic Robotic 3D Vision System. 1-3 - Sheng-Jung Yu, Yu-Chi Lee, Chia-Hsiang Yang:
A 1.18mW Double Ratchet Cryptographic Processor with Backward Secrecy for IoT Devices. 1-3 - Beomsoo Park, Changsok Han, Nima Maghari:
Correlated Dual-Loop Sturdy MASH CT ΔΣ ADC with Indirect Signal Feedforward. 1-3 - Yong-Sik Kwak, Ho-Jin Kim, Kang-Il Cho, Jun-Ho Boo, Gil-Cho Ahn:
A 0.9V 0.022mm2 103dB DR Switched-Capacitor Audio Delta-Sigma Modulator Using Input-Referred kT/C Noise Reduction Technique. 1-3 - Hyeyeon Lee, Changuk Lee, Jae-Youl Lee, Yoon-Kyung Choi, Youngcheol Chae:
A 0.033-mm2 21.5-aF Resolution Continuous-Time Delta-Sigma Capacitance-to-Digital Converter with Parasitic Capacitance Immunity up to 480pF. 1-3 - Kasho Yamamoto, Takashi Takemoto, Chihiro Yoshimura, Mayumi Mashimo, Masanao Yamaoka:
A 1.3-Mbit Annealing System Composed of Fully-Synchronized 9-board x 9-chip x 16-kbit Annealing Processor Chips for Large-Scale Combinatorial Optimization Problems. 1-3 - Shifu Wu, K. De Silva, Snehlata Gutgutia, Bevan M. Baas, Massimo Alioto:
A 1448-Mpixel/s, 84-pJ/Pixel Display Stream Compression Encoder in 28 nm for 4K Video Resolution. 1-3 - Masoud Pashaeifar, Anil Kumar Kumaran, Mohammadreza Beikmirza, Leo C. N. de Vreede, Morteza S. Alavi:
A 24-to-32GHz series-Doherty PA with two-step impedance inverting power combiner achieving 20.4dBm Psat and 38%/34% PAE at Psat/6dB PBO for 5G applications. 1-3 - Shenggao Li, Chien-Chun Tsai, Eric Soenen, Frank J. C. Lee, Cheng-Hsiang Hsieh:
Energy Efficient Design Through Design and Technology Co-Optimization Near the Finish Line of CMOS Scaling. 1-3 - Kwangho Lee, Woosong Jung, Haram Ju, Jinhyung Lee, Deog-Kyoon Jeong:
A 48 Gb/s PAM4 receiver with Baud-rate phase-detector for multi-level signal modulation in 40 nm CMOS. 1-3 - Chi-Wa U, Man-Kay Law, Chi-Seng Lam, Rui Paulo Martins:
Auto-Calibration Technique for Current-Based Bandgap Voltage Reference. 1-3 - Kye-Seok Yoon, Hye-Bong Ko, Jin-Woo So, Sung-Woo Lee, Sung-Kyu Cho, Woon-Hyung Heo, Ho-Sung Son, Seung-Hoon Kim, Dong-Joon Kim, Kwon-Yub Hyung, Dae-Woong Cho, Jung-Wook Heo, Hyoung-Seok Oh, Sung-Ung Kwak:
Zero Current Detector with Slope Judgement Calibration in Mobile Battery Charger IC. 1-3 - Sachin Kalia, Bichoy Bahr, Tolga Dinc, Baher Haroun, Swaminathan Sankaran:
An Ultra-Low Close-In Phase Noise Series-Resonance BAW Oscillator in a 130-nm BiCMOS process. 1-3 - Shinsuke Hara, Ruibing Dong, Sangyeop Lee, Kyoya Takano, Naoya Toshida, Satoru Tanoi, Tatsuo Hagino, Mohamed H. Mubarak, Norihiko Sekine, Issei Watanabe, Akifumi Kasamatsu, Kunio Sakakibara, Shunichi Kubo, Satoshi Miura, Yohtaro Umeda, Takeshi Yoshida, Shuhei Amakawa, Minoru Fujishima:
A 76-Gbit/s 265-GHz CMOS Receiver. 1-3 - Tai-Haur Kuo, Kuan-Yu Chen, Hsiao-Ping Lin, Shang-Jung Liu:
Self-powered light sensor for simultaneous intensity-and-direction sensing and maximum-energy harvesting with shared photodiodes. 1-3 - Masaya Nakano, Yoshinobu Kaneda, Koichi Takeda, Takahiro Shimoi, Yasunobu Aoki, Satoru Nakanishi, Yosuke Tashiro, Yasuhiko Taito, Ken Matsubara, Munekatsu Nakagawa, Tomoya Ogawa, Takashi Kurafuji, Hidenori Mitani, Takashi Ito, Takashi Kono:
A 40nm Embedded SG-MONOS Flash Macro for High-end MCU Achieving 200MHz Random Read Operation and 7.91Mb/mm2 Density with Charge Assisted Offset Cancellation Sense Amplifier. 1-3 - Pen-Jui Peng, Hsiang-En Huang, Wei-Chien Huang, Po-Lin Lee, Ming-Wei Lin, Ying-Zong Juang, Sheng-Hsiang Tseng:
A 56-Gb/s PAM-4 Optical Transceiver with Nonlinear FFE for VCSEL Driver in 40nm CMOS. 1-3 - Hyunmyung Oh, Hyungjun Kim, Daehyun Ahn, Jihoon Park, Yulhwa Kim, Inhwan Lee, Jae-Joon Kim:
Energy-efficient charge sharing-based 8T2C SRAM in-memory accelerator for binary neural networks in 28nm CMOS. 1-3 - Yuchuan Gong, Qingsong Liu, Luying Que, Conghan Jia, Jiahui Huang, Ye Liu, Jiayan Gan, Yuxiang Xie, Yong Zhou, Lili Liu, Xiaoqiang Xiang, Liang Chang, Jun Zhou:
RAODAT: An Energy-Efficient Reconfigurable AI-based Object Detection and Tracking Processor with Online Learning. 1-3 - Yuming He, Federico Corradi, Chengyao Shi, Ming Ding, Martijn Timmermans, Jan Stuijt, Pieter Harpe, Ilja Ocket, Yao-Hong Liu:
A 28.2 μC Neuromorphic Sensing System Featuring SNN-based Near-sensor Computation and Event-Driven Body-Channel Communication for Insertable Cardiac Monitoring. 1-3 - Chih-Cheng Chen, Chih-Cheng Hsieh:
A 12-ENOB Second-Order Noise Shaping SAR ADC with PVT-insensitive Voltage-Time-Voltage Converter. 1-3 - Jipeng Wang, Yi Zhan, Zhaoxu Wang, Zixuan Peng, Jiarui Xu, Bingqiang Liu, Guoyi Yu, Fengwei An, Chao Wang, Xuecheng Zou:
A Reconfigurable Matrix Multiplication Coprocessor with High Area and Energy Efficiency for Visual Intelligent and Autonomous Mobile Robots. 1-3 - Tomohiro Higuchi, Dai Suzuki, Ryo Ishida, Yasuaki Isshiki, Kazuki Arai, Kohei Onizuka, Kousuke Miyaji:
A 5.7GHz RF Wireless Power Transfer Receiver Using 84.5% Efficiency 12V SIDO Buck-Boost DC-DC Converter with Internal Power Supply Mode. 1-3 - Jiahao Liu, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins:
A 0.46pJ/bit Ultralow-Power Entropy-Preselection-Based Strong PUF with Worst-Case BER-6. 1-3 - Chih-Sheng Lin, Fu-Cheng Tsai, Jian-Wei Su, Sih-Han Li, Tian-Sheuan Chang, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Chih-I Wu, Tuo-Hung Hou:
A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration. 1-3 - Yang Jiang, Man-Kay Law, Pui-In Mak, Rui Paulo Martins:
An Arithmetic Progression Switched-Capacitor DC-DC Converter with Soft VCR Transitions Achieving 93.7% Peak Efficiency and 400 mA Output Current. 1-3 - Zule Xu:
A 0.79-1.16-GHz Synthesizable Fractional-N PLL Using DTC-Based Multi-Stage Injection with Dithering-Assisted Local Skew Calibration Achieving -232.8-dB FoMref. 1-3 - Jacob N. Rohan, Jaydeep P. Kulkarni:
Realizing Direct Convolution in Memory with Systolic-RAM. 1-3 - Hyungrok Do, Jung-Woo Sull, Seunghyun Lee, Kwangho Lee, Deog-Kyoon Jeong:
A 64 Gb/s 2.09 pJ/b PAM-4 VCSEL Transmitter with Bandwidth Extension Techniques in 40 nm CMOS. 1-3 - Peng Xu, Xueli Zhang, Peng Cao, Tingting Wei, Zhiguo Tong, Jiawei Xu, Zhiliang Hong:
A 2.7W AC-coupled hybrid supply modulator achieving 200MHz envelope-tracking bandwidth for 5G new radio power amplifier. 1-3 - Pingcheng Dong, Zhuoao Li, Zhuoyu Chen, Ruoheng Yao, Huanshihong Deng, Wenyue Zhang, Yangyi Zhang, Lei Chen, Chao Wang, Fengwei An:
A 139 fps pixel-level pipelined binocular stereo vision accelerator with region-optimized semi-global matching. 1-3 - Jongmin Lee, Yoonmyung Lee:
A current-integrated differential NAND-structured PUF for stable and V/T variation-tolerant low-cost IoT security. 1-3 - Ziyang Luo, Hoi Lee:
A 87.2%-Efficiency 27.12MHz Current-Mode Wireless Power Receiver with Ramp-Assisted Energy Delivery Controller for Implantable Devices. 1-3 - Shu-Yung Lin, Chin-Hsiang Liang, Kai-Syun Chang, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai:
A Multi-phase Series-Parallel with Bond Wire Auxiliary Fully-Integrated 250pF Switched-Capacitor with 13.6mV output ripple for Supplying Temperature Sensor with 0.1°C Accuracy to Early Detect COVID-19. 1-3 - Ziyu Li, Weiwei Shan, Chengjun Wu, Haitao Ge, Jun Yang:
An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator without Accuracy Loss in 28nm CMOS. 1-3 - Wooyoung Jo, Juhyoung Lee, Seunghyun Park, Hoi-Jun Yoo:
An Energy-Efficient Deep Reinforcement Learning FPGA Accelerator for Online Fast Adaptation with Selective Mixed-precision Re-training. 1-3 - Khoi T. Phan, Yue Chao, Howard C. Luong:
A 1.92GHz-3.84GHz 0.74ps-1.09ps-Jitter Inductor-less Injection-Locked Frequency Synthesizer with Automatic Frequency Selection and Timing Alignment. 1-3 - Ghil-Geun Oh, Min-Hye Ho, Yeon-Jung Shin, Jaewook Choi, Ju-Youn Kim, Young-Dae Kim:
Dynamic Voltage Stress Sensing Circuits for Screening Out Early Device Reliability Issues in Advanced Technology Nodes. 1-3 - Xiangrong Huang, Haikun Jia, Shengnan Dong, Wei Deng, Zhihua Wang, Baoyong Chi:
A 24-30GHz 4-Element Phased Array Transceiver with Low Insertion Loss Compact T/R Switch and Bidirectional Phase Shifter in 65 nm CMOS Technology. 1-3 - Saito Shibata, Reiji Miura, Yoshiki Sawabe, Kota Shiba, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
A 5-GHz 0.15-mm2 Collision Avoidable RFID Employing Complementary Pass-transistor Adiabatic Logic with an Inductively Connected External Antenna. 1-3 - Yu-Sian Liao, Wei-Zen Chen:
A Single-Channel 1.75GS/s, 6-Bit Flash-Assisted SAR ADC with Self-Adaptive Timer and On-Chip Offset Calibration. 1-3 - Canxing Piao, Yeonsoo Ahn, Donguk Kim, Jihoon Park, Jubin Kang, Minseok Shin, Kangbong Seo, Seong-Jin Kim, Jung-Hoon Chun, Jaehyuk Choi:
A 70mW Indirect Time-of-Flight Image Sensor with Depth Dynamic Range Enhancement and Fixed Depth Noise Compensation. 1-3 - Jeongwon Choe, Youngjoo Lee:
A 7Gbps (160, 80) Non-Binary LDPC Decoder with Dual-Message EMS Algorithm in 22nm FinFET Technology. 1-3 - Hyeon-Ji Choi, Joo-Mi Cho, Hyo-Jin Park, Sung-Wan Hong:
An Output Capacitor-less Low-dropout Regulator using a Wide-range Single-stage Gain-boosted Error Amplifier and a Frequency-dependent Buffer with a Total Compensation Capacitance of 2.5 pF in 0.5 µm CMOS. 1-3 - Jincheng Zhang, Tianxiang Wu, Yong Chen, Junyan Ren, Shunli Ma:
A 3-to-78GHz Differential Distributed Amplifier with Ultra- Balanced Active Balun and Gain Boosting Techniques in 65-nm CMOS Process. 1-3 - Weihong Yan, Yuxin Ji, Ce Ma, Lining Hu, Yang Zhao, Yongfu Li, Guoxing Wang, Yong Lian:
A Computationally Efficient, Hardware Re-configurable Architecture for QRS Detection and ECG authentication. 1-2 - Yoontae Jung, Soon-Jae Kweon, Hyuntak Jeon, Taeju Lee, Injun Choi, Kyeongwon Jeong, Mi Kyung Kim, Hyunjoo Jenny Lee, Sohmyung Ha, Minkyu Je:
A 99.5dB-DR 5kHz-BW Closed-Loop Neural-Recording IC based on Continuous-Time Dynamic-Zoom ΔΣ ADC with Automatic AFE-Gain Control. 1-3 - Pingda Guan, Haikun Jia, Wei Deng, Zhihua Wang, Baoyong Chi:
A 33.5-37.5 GHz 4-Element Phased-Array Transceiver Front-End with High-Accuracy Low-Variation 6-bit Resolution 360° Phase Shift and 0~31.5 dB Gain Control in 65 nm CMOS. 1-3 - Chun-Yu Lin, Yu-Wei Huang, Tsung-Hsien Lin:
A ± 20-ppm -50°C-105°C 1-µA 32.768-kHz Clock Generator with a System-HFXO-Assisted Background Calibration. 1-3 - Zhao-yang Liu, Feng Qi, Yelong Wang, Pengxiang Liu, Wei-fan Li:
A 150-to-1050 GHz Terahertz Detector in 65 nm CMOS. 1-3 - Tao Xia, Xuefeng Chen, Yuwei Wang, Yuan Li, Yifan Wu, Lei Wang, Liujia Song, Shenglong Zhuo, Zhihong Lin, Patrick Yin Chiang:
An integrated 8A pulsed VCSEL array driver under 12V supply with built-in pulse monitor and automatic peak current control for direct time-of-flight applications. 1-3 - Keun-Mok Kim, Hyun-Gi Seok, Jeong-Il Seo, Kyung-Sik Choi, Sang-Gug Lee:
0.6 V 8.1/0.2µW Ultra-Low-Power Logarithmic Power Detectors Employing Subthreshold MOS Transistors. 1-3 - Alican Çaglar, Steven Van Winckel, Steven Brebels, Piet Wambacq, Jan Craninckx:
A 4.2mW 4K 6-8GHz CMOS LNA for Superconducting Qubit Readout. 1-3 - Ya-Yun Hou, Shaopeng Lai, Hung-Kun Chang, Yun-Wen Lu, Hsie-Chia Chang:
A 45.4x∼221.2x latency Improvement of SRP-5 Cryptographic Engine for Smart Grid Network. 1-3 - Woojin Ahn, Doohee Kim, Jonghyeok Park, Jeong Hoan Park, Taeju Lee, Kyeong-Won Jeon, Kyou Sik Min, Hoseung Lee, Minkyu Je:
A Neural Stimulation IC Based on a Reconfigurable Current DAC with In-Situ Neural Recording Function for Cochlear Implant Systems. 1-3 - Yu-Sian Lu, Cheng-Lung Lee, Wei-Zen Chen:
A 10 GHz Dual-Loop PLL with Active Noise Cancellation Achieving 12dB Spur and 29% Noise Reduction. 1-2 - Zexue Liu, Yi Tan, Chen Xu, Heyi Li, Haoyun Jiang, Xinyu Bao, Dong Wang, Junhua Liu, Huailin Liao:
A 2.85mm2 RF Transceiver in 40nm CMOS for IoT Micro-Hub Applications. 1-3 - Jixuan Li, Jiabao Chen, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins:
A 50.4 GOPs/W FPGA-Based MobileNetV2 Accelerator using the Double-Layer MAC and DSP Efficiency Enhancement. 1-3 - Yizhuo Wang, Tenghao Zou, Bowen Chen, Shujiang Ji, Chao Zhang, Na Yan:
A 7.9-14.3GHz -243.3dB FoMT Sub-Sampling PLL with Transformer-Based Dual-Mode VCO in 40nm CMOS. 1-3
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