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2020 – today
- 2021
[j44]Michael Conrad Meyer
, Yu Wang, Takahiro Watanabe:
Real-Time Cost Minimization of Fog Computing in Mobile-Base-Station Networked Disaster Areas. IEEE Open J. Comput. Soc. 2: 53-61 (2021)- [j43]Itsuo Takanami, Masaru Fukushi, Takahiro Watanabe:
Self-restructuring of Mesh-Connected Processor Arrays with Spares Assigned on Rotated Orthogonal Side. Trans. Comput. Sci. 38: 36-53 (2021) - 2020
- [j42]Tingyu Zhou, Tieyuan Pan, Michael Conrad Meyer, Yiping Dong, Takahiro Watanabe:
A Fast Online Task Placement Algorithm for Three-Dimensional Dynamic Partial Reconfigurable Devices. IEEE Access 8: 36903-36918 (2020) - [j41]Tingyu Zhou, Tieyuan Pan, Michael Conrad Meyer, Yiping Dong, Takahiro Watanabe:
Multi-Shape Task Placement Algorithm Based on Low Fragmentation Resource Management on 2D Heterogeneous Dynamic Partial Reconfigurable Devices. IEEE Access 8: 186362-186375 (2020) - [j40]Takuya Iimura, Toshimasa Maruta, Takahiro Watanabe:
Two-person pairwise solvable games. Int. J. Game Theory 49(2): 385-409 (2020) - [j39]Hidehiko Yamamoto, Takahiro Watanabe, Takayoshi Yamada:
Selection System of Robot Type for Cell Assembly Production (Production Efficiency Comparison of Single and Double Arm Robot). J. Robotics Netw. Artif. Life 7(2): 77-80 (2020) - [c49]Tingyu Zhou, Tieyuan Pan, Michael Conrad Meyer, Yiping Dong, Takahiro Watanabe:
An Interval-based Mapping Algorithm for Multi-shape Tasks on Dynamic Partial Reconfigurable FPGAs. IPDPS Workshops 2020: 127-130
2010 – 2019
- 2019
- [j38]Huatao Zhao, Xu Jia, Takahiro Watanabe:
Filter router: An enhanced router design for efficient stacked shared cache network. IEICE Electron. Express 16(14): 20190358 (2019) - [j37]Huatao Zhao, Jiongyao Ye, Takahiro Watanabe:
A Low-power Shared Cache Design with Modified PID Controller for Efficient Multicore Embedded Systems. J. Inf. Process. 27: 149-158 (2019) - [c48]Michael Conrad Meyer, Yu Wang, Takahiro Watanabe:
Wavelength-Selective Fog-Computing Network for Big-Data Analytics of Wireless Data. ICEIC 2019: 1-7 - [c47]Toshihiro Komiyama, Shigeo Konno, Takahiro Watanabe, Shigenori Matsui, Masakazu Kase, Issei Igarashi:
Improvement of Agile Software Development Process Based on Automotive SPICE: A Case Study. EuroSPI 2019: 518-531 - [c46]Zhengqian Han, Michael Conrad Meyer, Xin Jiang, Takahiro Watanabe:
Low-Cost Congestion Detection Mechanism for Networks-on-Chip. MCSoC 2019: 157-163 - [c45]Michael Conrad Meyer, Yu Wang, Takahiro Watanabe:
Fault-Tolerant Traffic-Aware Routing Algorithm for 3-D Photonic Networks-on-Chip. MCSoC 2019: 172-179 - [c44]Siying Xu, Michael Conrad Meyer, Xin Jiang, Takahiro Watanabe:
A Traffic-Robust Routing Algorithm for Network-on-Chip Systems. MCSoC 2019: 209-216 - [c43]Yaoying Luo, Michael Conrad Meyer, Xin Jiang, Takahiro Watanabe:
A Hotspot-Pattern-Aware Routing Algorithm for Networks-on-Chip. MCSoC 2019: 229-235 - 2018
- [j36]Takuya Iimura, Pierre von Mouche, Takahiro Watanabe:
Binary action games: Deviation properties, semi-strict equilibria and potentials. Discret. Appl. Math. 251: 57-68 (2018) - [c42]Tingyu Zhou, Tieyuan Pan, Zhiguo Bao, Takahiro Watanabe:
A Time-based Leakage-aware Algorithm for Task Placement and Scheduling Problem on Dynamic Reconfigurable FPGA. ICSAI 2018: 501-506 - [c41]Jindun Dai, Renjie Li, Xin Jiang, Takahiro Watanabe:
PDA-HyPAR: Path-diversity-aware hybrid planar adaptive routing algorithm for 3D NoCs. ISQED 2018: 131-137 - [c40]Takahiro Watanabe, Hitoshi Iima:
Nonlinear Optimization Method Based on Stochastic Gradient Descent for Fast Convergence. SMC 2018: 4198-4203 - 2017
- [j35]Xin Jiang, Xiangyang Lei, Lian Zeng, Takahiro Watanabe:
High Performance Virtual Channel Based Fully Adaptive 3D NoC Routing for Congestion and Thermal Problem. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(11): 2379-2391 (2017) - [c39]Jindun Dai, Xin Jiang, Takahiro Watanabe:
An adaptive routing algorithm based on network partitioning for 3D Network-on-Chip. CITS 2017: 229-233 - [c38]Tomoo Ushio, Shigeharu Shimamura, Hiroshi Kikuchi, Fumihiko Mizutani, Kenichi Naito, Takahiro Watanabe, Masakazu Wada, Nobuhiro Takahashi:
Osaka urban phased array radar network experiment. IGARSS 2017: 5966-5968 - [c37]Jindun Dai, Wenda Ma, Xin Jiang, Takahiro Watanabe:
Hybrid path-diversity-dominant output selection method for Network-on-Chip systems. ISOCC 2017: 125-126 - [c36]Xin Jiang, Xiangyang Lei, Lian Zeng, Takahiro Watanabe:
High performance virtual channel based fully adaptive thermal-aware routing for 3D NoC. ISQED 2017: 289-295 - [c35]Jindun Dai, Xin Jiang, Renjie Li, Takahiro Watanabe:
An Efficient Deadlock-Free Adaptive Routing Algorithm for 3D Network-on-Chips. MCSoC 2017: 29-36 - 2016
- [j34]Lian Zeng, Tieyuan Pan, Xin Jiang, Takahiro Watanabe:
An Efficient Highly Adaptive and Deadlock-Free Routing Algorithm for 3D Network-on-Chip. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(7): 1334-1344 (2016) - [j33]Tieyuan Pan, Li Zhu, Lian Zeng, Takahiro Watanabe, Yasuhiro Takashima:
An Online Task Placement Algorithm Based on MER Enumeration for Partially Reconfigurable Device. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(7): 1345-1354 (2016) - [j32]Tieyuan Pan, Lian Zeng, Yasuhiro Takashima, Takahiro Watanabe:
A Fast MER Enumeration Algorithm for Online Task Placement on Reconfigurable FPGAs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2412-2424 (2016) - [j31]Takuya Iimura, Takahiro Watanabe:
Pure strategy equilibrium in finite weakly unilaterally competitive games. Int. J. Game Theory 45(3): 719-729 (2016) - [c34]Shunki Itadera, Takahiro Watanabe, Yasuhisa Hasegawa, Toshio Fukiida, Masanori Tanimoto, Izumi Kondo:
Coordinated movement algorithm for accompanying cane robot. MHS 2016: 1-3 - 2015
- [j30]Ran Zhang, Tieyuan Pan, Li Zhu, Takahiro Watanabe:
Layer Assignment and Equal-length Routing for Disordered Pins in PCB Design. Inf. Media Technol. 10(3): 395-404 (2015) - [j29]Lian Zeng, Xin Jiang, Takahiro Watanabe:
A Performance Enhanced Dual-switch Network-on-chip Architecture. Inf. Media Technol. 10(3): 405-414 (2015) - [j28]Ran Zhang, Tieyuan Pan, Li Zhu, Takahiro Watanabe:
Layer Assignment and Equal-length Routing for Disordered Pins in PCB Design. IPSJ Trans. Syst. LSI Des. Methodol. 8: 75-84 (2015) - [j27]Lian Zeng, Xin Jiang, Takahiro Watanabe:
A Performance Enhanced Dual-switch Network-on-chip Architecture. IPSJ Trans. Syst. LSI Des. Methodol. 8: 85-94 (2015) - [c33]Lian Zeng, Takahiro Watanabe:
A performance enhanced dual-switch Network-on-Chip architecture. ASP-DAC 2015: 69-74 - [c32]Ran Zhang, Tieyuan Pan, Li Zhu, Takahiro Watanabe:
A length matching routing method for disordered pins in PCB design. ASP-DAC 2015: 402-407 - [c31]Huatao Zhao, Jiongyao Ye, Xian Su, Takahiro Watanabe:
Application-specific shared last-level cache optimization for low-power embedded systems. NEWCAS 2015: 1-4 - 2014
- [j26]Takuya Iimura, Takahiro Watanabe:
Existence of a pure strategy equilibrium in finite symmetric games where payoff functions are integrally concave. Discret. Appl. Math. 166: 26-33 (2014) - [j25]Xin Jiang, Lian Zeng, Takahiro Watanabe:
A Sophisticated Routing Algorithm in 3D NoC with Fixed TSVs for Low Energy and Latency. Inf. Media Technol. 9(4): 404-412 (2014) - [j24]Xin Jiang, Lian Zeng, Takahiro Watanabe:
A Sophisticated Routing Algorithm in 3D NoC with Fixed TSVs for Low Energy and Latency. IPSJ Trans. Syst. LSI Des. Methodol. 7: 101-109 (2014) - [c30]Tieyuan Pan, Ran Zhang, Yasuhiro Takashima, Takahiro Watanabe:
A randomized algorithm for the fixed-length routing problem. APCCAS 2014: 711-714 - 2013
- [j23]Xin Jiang, Ran Zhang, Takahiro Watanabe:
An Efficient Algorithm for 3D NoC Architecture Optimization. Inf. Media Technol. 8(2): 254-261 (2013) - [j22]Xin Jiang, Ran Zhang, Takahiro Watanabe:
An Efficient Algorithm for 3D NoC Architecture Optimization. IPSJ Trans. Syst. LSI Des. Methodol. 6: 34-41 (2013) - [c29]Ran Zhang, Xue Wei, Takahiro Watanabe:
A sorting-based IO connection assignment for flip-chip designs. ASICON 2013: 1-4 - [c28]Huatao Zhao, Jiongyao Ye, Yuxin Sun, Takahiro Watanabe:
Pseudo Dual Path Processing to reduce the branch misprediction penalty in embedded processors. ASICON 2013: 1-4 - [c27]Takashi Yoza, Retsu Moriwaki, Yuki Torigai, Yuki Kamikubo, Takayuki Kubota, Takahiro Watanabe, Takumi Fujimori, Hiroyuki Ito, Masato Seo, Kouta Akagi, Yuichiro Yamaji, Minoru Watanabe:
FPGA Blokus Duo Solver using a massively parallel architecture. FPT 2013: 494-497 - 2012
- [j21]Ce Li, Yiping Dong, Takahiro Watanabe:
Region-Oriented Placement Algorithm for Coarse-Grained Power-Gating FPGA Architecture. IEICE Trans. Inf. Syst. 95-D(2): 314-323 (2012) - [j20]Ce Li, Yiping Dong, Takahiro Watanabe:
Region Oriented Routing FPGA Architecture for Dynamic Power Gating. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2199-2207 (2012) - [j19]Jiongyao Ye, Hongfeng Ding, Yingtao Hu, Takahiro Watanabe:
A Behavior-based Adaptive Access-mode for Low-power Set-associative Caches in Embedded Systems. Inf. Media Technol. 7(1): 1-11 (2012) - [j18]Jiongyao Ye, Hongfeng Ding, Yingtao Hu, Takahiro Watanabe:
A Behavior-based Adaptive Access-mode for Low-power Set-associative Caches in Embedded Systems. J. Inf. Process. 20(1): 26-36 (2012) - [j17]Takahiro Watanabe, Minoru Watanabe:
0.18 μm CMOS proess high-sensitivity optially reonfgurable gatearray VLSI. SIGARCH Comput. Archit. News 40(5): 82-86 (2012) - [c26]Takahiro Watanabe, Minoru Watanabe:
Triple Module Redundancy of a Laser Array Driver Circuit for Optically Reconfigurable Gate Arrays. ARC 2012: 163-173 - [c25]Takahiro Watanabe, Minoru Watanabe:
High Speed - Low Power Optical Configuration on an ORGA with a Phase-modulation Type Holographic Memory. IPDPS Workshops 2012: 256-260 - [c24]Takahiro Watanabe, Minoru Watanabe:
0.18-um CMOS Process Highly Sensitive Differential Optically Reconfigurable Gate Array VLSI. ISVLSI 2012: 308-313 - [c23]Takahiro Watanabe, Minoru Watanabe:
Inversion/non-inversion reconfiguration scheme for a 0.18 J.1m CMOS process optically reconfigurable gate array VLSI. MWSCAS 2012: 117-120 - 2011
- [j16]Zhiguo Bao, Fangfang Wang, Xiaoming Zhao, Takahiro Watanabe:
Fault-tolerant image filter design using particle swarm optimization. Artif. Life Robotics 16(3): 333-337 (2011) - [j15]Jiongyao Ye, Yingtao Hu, Hongfeng Ding, Takahiro Watanabe:
Analysis before Starting an Access: A New Power-Efficient Instruction Fetch Mechanism. IEICE Trans. Inf. Syst. 94-D(7): 1398-1408 (2011) - [j14]Jiongyao Ye, Yu Wan, Takahiro Watanabe:
An Adaptive Various-Width Data Cache for Low Power Design. IEICE Trans. Inf. Syst. 94-D(8): 1539-1546 (2011) - [j13]Ce Li, Yiping Dong, Takahiro Watanabe:
Low Power Placement and Routing for the Coarse-Grained Power Gating FPGA Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2519-2527 (2011) - [j12]Jiongyao Ye, Yu Wan, Takahiro Watanabe:
A New Recovery Mechanism in Superscalar Microprocessors by Recovering Critical Misprediction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2639-2648 (2011) - [c22]Jiongyao Ye, Jiannan Jin, Takahiro Watanabe:
A behavior-based reconfigurable cache for the low-power embedded processor. ASICON 2011: 1-5 - [c21]Xin Jiang, Ran Zhang, Takahiro Watanabe:
An efficient design algorithm for exploring flexible topologies in custom adaptive 3D NoCs for high performance and low power. ASICON 2011: 535-538 - [c20]Takahiro Watanabe, Minoru Watanabe:
Dependable Optically Reconfigurable Gate Array with a Phase-Modulation Type Holographic Memory. FPL 2011: 34-37 - [c19]Takahiro Watanabe, Retsu Moriwaki, Yuichiro Yamaji, Yuki Kamikubo, Yuki Torigai, Yuki Nihira, Takashi Yoza, Yumiko Ueno, Yuji Aoyama, Minoru Watanabe:
An FPGA Connect6 Solver with a two-stage pipelined evaluation. FPT 2011: 1-4 - [c18]Yiwen Su, Zhiguo Bao, Fangfang Wang, Takahiro Watanabe:
Efficient GA Approach Combined with Taguchi Method for Mixed Constrained Circuit Design. ICCSA Workshops 2011: 290-293 - [c17]Ce Li, Yiping Dong, Takahiro Watanabe:
New power-aware placement for region-based FPGA architecture combined with dynamic power gating by PCHM. ISLPED 2011: 223-228 - [c16]Mayumi Ueda, Takuya Funatomi, Atsushi Hashimoto, Takahiro Watanabe, Michihiko Minoh:
Developing a Real-Time System for Measuring the Consumption of Seasoning. ISM 2011: 393-398 - 2010
- [j11]Zhiguo Bao, Takahiro Watanabe:
Mixed constrained image filter design using particle swarm optimization. Artif. Life Robotics 15(3): 363-368 (2010) - [j10]Zhiguo Bao, Takahiro Watanabe:
Erratum to: Mixed constrained image filter design using particle swarm optimization. Artif. Life Robotics 15(4): 571 (2010) - [j9]Zhiguo Bao, Takahiro Watanabe:
Circuit Design Optimization Using Genetic Algorithm with Parameterized Uniform Crossover. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(1): 281-290 (2010) - [c15]Zhen Lin, Yiping Dong, Yan Li, Takahiro Watanabe:
A hybrid architecture for efficient FPGA-based implementation of multilayer neural network. APCCAS 2010: 616-619 - [c14]Takayuki Mabuchi, Takahiro Watanabe, Retsu Moriwaki, Yuji Aoyama, Amarjargal Gundjalam, Yuichiro Yamaji, Hironari Nakada, Minoru Watanabe:
Othello Solver based on a soft-core MIMD processor array. FPT 2010: 511-514 - [c13]Yiping Dong, Zhen Lin, Yan Li, Takahiro Watanabe:
High performance implementation of Neural Networks by networks on chip with 5-port 2-virtual channels. ISCAS 2010: 381-384
2000 – 2009
- 2009
- [j8]Zhiguo Bao, Takahiro Watanabe:
A novel genetic algorithm with different structure selection for circuit design optimization. Artif. Life Robotics 14(2): 266-270 (2009) - [c12]Zhiguo Bao, Takahiro Watanabe:
A Novel Genetic Algorithm with Cell Crossover for Circuit Design Optimization. ISCAS 2009: 2982-2985 - 2008
- [c11]Ce Li, Yang Jiang, Zhenyu Wu, Takahiro Watanabe:
A Multiprocessor System for a Small Size Soccer Robot Control System. DELTA 2008: 115-118 - 2007
- [j7]Masaya Takahashi, Takahiro Watanabe, Takeshi Yoshimura:
Score Sequence Pair Problems of (r11, r12, r22)-Tournaments - - Determination of Realizability - - . IEICE Trans. Inf. Syst. 90-D(2): 440-448 (2007) - [j6]Yusuke Suzuki, Takahiro Watanabe:
Generating even triangulations of the projective plane. J. Graph Theory 56(4): 333-349 (2007) - [c10]Masaya Takahashi, Takahiro Watanabe, Takeshi Yoshimura:
Construction of an (r11, r12, r22)-Tournament from a Score Sequence Pair. ISCAS 2007: 3403-3406 - 2006
- [c9]Masaya Takahashi, Takahiro Watanabe, Takeshi Yoshimura:
Realizability of Score Sequence Pair of an (r1l, r12, r22)-Tournament. APCCAS 2006: 1019-1022 - [c8]Takahiro Watanabe, Yasunobu Nohara, Kensuke Baba, Sozo Inoue, Hiroto Yasuura:
On Authentication between Human and Computer. PerCom Workshops 2006: 636-639 - 2005
- [c7]Takahiro Watanabe, Sozo Inoue, Hiroto Yasuura, Jun Sasaki, Yasushi Aoki, Kazumi Akimoto:
An RFID-based multi-service system for supporting conference events. AMT 2005: 435-439 - 2001
- [c6]Tomomi Matsui, Takahiro Watanabe:
Sealed Bid Mulit-object Auctions with Necessary Bundles and Its Application to Spectrum Auctions. PRIMA 2001: 78-92
1990 – 1999
- 1999
- [j5]Takahiro Watanabe, Masahiko Yachida:
Real-time gesture recognition using eigenspace from multi-input imagesequences. Syst. Comput. Jpn. 30(13): 61-72 (1999) - 1998
- [j4]Takahiro Watanabe, Chil-Woo Lee, Masahiko Yachida:
Real-time gesture recognition from dynamic images for construction of any interactive system: Application to a virtual conductor system. Syst. Comput. Jpn. 29(5): 62-72 (1998) - [c5]Takahiro Watanabe, Masahiko Yachida:
Real Time Gesture Recognition Using Eigenspace from Multi Input Image Sequence. FG 1998: 428-435 - [c4]Takahiro Watanabe, Masahiko Yachida:
Real time recognition of gesture and gesture degree information using multi input image sequences. ICPR 1998: 1855-1858 - 1997
- [c3]Takahiro Watanabe, Masahiko Yachida:
Real-time gesture recognition using KL expansion of image sequence. IROS 1997: 973-979 - 1996
- [c2]Takahiro Watanabe, Chil-Woo Lee, Akitoshi Tsukamoto, Masahiko Yachida:
Real-Time Gesture Recognition Using Maskable Template Model. ICMCS 1996: 341-348 - [c1]Qin Luo, Takahiro Watanabe, Takeshi Nakayama:
Identifying contents page of documents. ICPR 1996: 696-700 - 1993
- [j3]Itsuo Takanami, Katsushi Inoue, Takahiro Watanabe, Minoru Oka:
Construction of fault-tolerant mesh-connected highly parallel computer and its performance analysis. Syst. Comput. Jpn. 24(8): 11-24 (1993)
1980 – 1989
- 1983
- [j2]Takao Nishizeki, Takao Asano, Takahiro Watanabe:
An approximation algorithm for the hamiltonian walk problem on maximal planar graphs. Discret. Appl. Math. 5(2): 211-222 (1983) - 1980
- [j1]Takao Asano, Takao Nishizeki, Takahiro Watanabe:
An upper bound on the length of a Hamiltonian walk of a maximal planar graph. J. Graph Theory 4(3): 315-336 (1980)
Coauthor Index
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